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Exam (elaborations)
Vlsi |152 Questions | With All Passed Answers 2024!!
Vlsi |152 Questions | With All Passed Answers 2024!!
Exam (elaborations)
Vlsi Final Exam Questions And Correct Answers
PopularVlsi Final Exam Questions And Correct Answers...
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VLSI Bundled Exam Questions WITH CORRECT Answers
VLSI Bundled Exam Questions WITH CORRECT Answers
Exam (elaborations)
VLSI Testing and Design for Testability UPDATED ACTUAL Exam Questions and CORRECT Answers
VLSI Testing and Design for Testability 
UPDATED ACTUAL Exam Questions and 
CORRECT Answers 
Logic Verification - CORRECT ANSWER 
accurately. 
Silicon Debug - CORRECT ANSWER 
Manufacturing Test - CORRECT ANSWER 
quality. 
Fault Models - CORRECT ANSWER 
Observability - CORRECT ANSWER 
Controllability - CORRECT ANSWER 
Design for Test - CORRECT ANSWER 
effective. 
Scan Design - CORRECT ANSWER 
controllability. 
BIST - CORRECT ANSWER - Ensures chip perfor...
Exam (elaborations)
Test of VLSI 1 UPDATED ACTUAL Exam Questions and CORRECT Answers
Test of VLSI 1 UPDATED ACTUAL Exam 
Questions and CORRECT Answers 
functional test - CORRECT ANSWER - development errors : 
correct functionality of the modules is tested in a functional test; a high 
coverage of the fault is targeted, leading to a long test process 
structural test - CORRECT ANSWER - physical or manufacturing defects: 
the presence of all signal lines, and their ability to carry 0 and 1s is 
checked in a structural test 
Verification - CORRECT ANSWER - Predic...
Exam (elaborations)
Test of VLSI 2 UPDATED ACTUAL Exam Questions and CORRECT Answers
Test of VLSI 2 UPDATED ACTUAL Exam 
Questions and CORRECT Answers 
Defect - CORRECT ANSWER 
hardware 
and its intended design - hardware, physical level 
error - CORRECT ANSWER 
fault - CORRECT ANSWER 
fault model - CORRECT ANSWER - unintended difference between the implemented - wrong output signal produced by a defective system - representation of a defect at the abstracted function leve
Exam (elaborations)
Test of VLSI 4 UPDATED ACTUAL Exam Questions and CORRECT Answers
Test of VLSI 4 UPDATED ACTUAL Exam 
Questions and CORRECT Answers 
Purpose of testability measure - CORRECT ANSWER 
inexpensive method to quantify 
how hard it is to set or observe internal signals of a circuit 
Controllability - CORRECT ANSWER - Need to have a computationally - difficulty of setting a particular signal to logic 0 
or 1 
Observability - CORRECT ANSWER 
signal 
Testability analysis - CORRECT ANSWER 
Controllability/Observability 
Analysis Program) - diff...
Exam (elaborations)
VLSI Circuit Testing Phases and Techniques UPDATED ACTUAL Exam Questions and CORRECT Answers
VLSI Circuit Testing Phases and Techniques 
UPDATED ACTUAL Exam Questions and 
CORRECT Answers 
Prototype Testing - CORRECT ANSWER 
under microscope. 
Visual Inspection - CORRECT ANSWER 
Fault Localization - CORRECT ANSWER 
Process Induced Faults - CORRECT ANSWER 
like pin-holes. 
Design Faults - CORRECT ANSWER 
contacts. - Initial evaluation of first prototype wafers - Microscopic examination of circuits for faults. - Identifying and pinpointing faults in circuits. - ...
Exam (elaborations)
VLSI chapter 1 UPDATED ACTUAL Exam Questions and CORRECT Answers
VLSI chapter 1 UPDATED ACTUAL Exam 
Questions and CORRECT Answers 
SSI - CORRECT ANSWER 
MSI - CORRECT ANSWER 
LSI - CORRECT ANSWER 
VLSI - CORRECT ANSWER 
Memory, DSP 
ULSI - CORRECT ANSWER - 10 gates , 60s , gates and op amps - 100-1000 gates , 70s , filters - 1000-10,000, 80s, microprocessors and A-D - 10,000-100,000 gates ,90's - 10,00,000-1,00,00,000 gates (~ 1million -10 million gates
Exam (elaborations)
VLSI chapter 1 UPDATED Exam Questions and CORRECT Answers
VLSI chapter 1 UPDATED Exam 
Questions and CORRECT Answers 
IC - CORRECT ANSWER - Integrated Circuit 
incorporates and interconnects a multiude of miniature electronic devices (transistors) on a single 
piece of SD material (silicon) 
pad - CORRECT ANSWER - connector on a die that is intended to be wired or otherwise 
electrically connected to a package pin. 
PCB - CORRECT ANSWER 
Die size - CORRECT ANSWER 
GE - CORRECT ANSWER 
four MOSFETs in static CMOS 
MOSFET - C...
Exam (elaborations)
VLSI Testing UPDATED ACTUAL Exam Questions and CORRECT Answers
VLSI Testing UPDATED ACTUAL Exam 
Questions and CORRECT Answers 
Yield - CORRECT ANSWER 
Reject Rate - CORRECT ANSWER 
Quality - CORRECT ANSWER - Acceptable parts divided by total parts fabricated. - Faulty parts passing final test divided by total. - Working parts passing final test divided by total. 
Quality Formula - CORRECT ANSWER - Quality equals 1 minus reject rate. 
Yield estimation according to Poisson - CORRECT ANSWER 
defect density and A is chip area 
Yield es...
Exam (elaborations)
VLSI Exam 1 UPDATED Exam Questions and CORRECT Answers
VLSI Exam 1 UPDATED Exam Questions 
and CORRECT Answers 
When two 2Y/4Y transistors are connected in series its equivalent resistance can be calculated 
from a single transistor with size: - CORRECT ANSWER - 4Y/4Y 
*cannot reduce* 
When two 2Y/4Y transistors are connected in parallel its equivalent resistance can be calculated 
from a single transistor with size: - CORRECT ANSWER - 2Y/8Y 
The starting material of the n-well process is: - CORRECT ANSWER 
type substrate - lightly...
Exam (elaborations)
CMOS VLSI Design Exam 1 UPDATED ACTUAL Exam Questions and CORRECT Answers
CMOS VLSI Design Exam 1 UPDATED 
ACTUAL Exam Questions and CORRECT 
Answers 
n type - CORRECT ANSWER - A class of extrinsic semiconductors containing dopant 
atoms with more than four valence electrons, allowing for extra electrons to provide more 
conductivity 
p type - CORRECT ANSWER - A class of extrinsic semiconductors containing dopant 
atoms with fewer than four valence electrons., has a "hole" that decreases conductivity. acts as a 
positive carrier 
diode - CORRECT ...
Exam (elaborations)
VLSI Final Exam Review UPDATED ACTUAL Exam Questions and CORRECT Answers
VLSI Final Exam Review UPDATED 
ACTUAL Exam Questions and CORRECT 
Answers 
What does the mobility in MOS mean and what is the general relation between NMOS and 
PMOS mobility? - CORRECT ANSWER - Mobility means how fast the electrons/holes 
move in a semiconductor 
What is the relation between MOS gate's 
i) length & resistance? 
ii) width and resistance? - CORRECT ANSWER 
the channel increases. - i) when length increases, resistance of 
ii) when width increases, resistance...
Exam (elaborations)
VLSI Design UPDATED ACTUAL Exam Questions and CORRECT Answers
VLSI Design UPDATED ACTUAL Exam 
Questions and CORRECT Answers 
Erste Maxwell - CORRECT ANSWER 
Spannung aus E-Feld - CORRECT ANSWER 
Gate-Bulk-Modes - CORRECT ANSWER - ε_0 * E_z(z) = ∫ρ dz - φ_z(z) = - ∫ E_z(z) dz - 1. Accumulation: V_GB = 0 
The majority carriers accumulate under the gate electrode due to certain 2nd order effects. 
2. Flat Band Voltage: V_GB = V_FB 
The majority carriers are repelled from the gate. They are distributed evenly in the bulk. 
3. Depletio...
Exam (elaborations)
VLSI Design UPDATED Exam Questions and CORRECT Answers
VLSI Design UPDATED Exam Questions 
and CORRECT Answers 
How would you define VLSI or very large scale integration? - CORRECT ANSWER - 
VLSI is essentially just a process that you use to create integrated circuits by incorporating 
millions of MOS transistors onto a single chip. These ICs are necessary for engineering 
integrated circuit microchips. You can then use the microchips for a wide variety of tools, like 
telecommunication technologies and semiconductors
Exam (elaborations)
Digital VLSI - Hardware Section UPDATED ACTUAL Exam Questions and CORRECT Answers
Digital VLSI - Hardware Section UPDATED 
ACTUAL Exam Questions and CORRECT 
Answers 
What is the difference between a RISC and CISC architecture? - CORRECT ANSWER - ● 
RISC architecture has less number of instructions and these instructions are simple instructions 
(i.e. fixed length instructions, and less addressing modes). On the other hand, CISC architecture 
has more number of instructions and these instructions are complex in nature (i.e. variable length 
instructions, and more...
Exam (elaborations)
CPE 151-CMOS and VLSI design exam 1 UPDATED ACTUAL Exam Questions and CORRECT Answers
CPE 151-CMOS and VLSI design exam 1 
UPDATED ACTUAL Exam Questions and 
CORRECT Answers 
MOSFET stand for: - CORRECT ANSWER 
Transistor - Metal Oxide Semiconductor Field Effect 
p-type semiconductor has ________ as majority charge carriers - CORRECT ANSWER 
holes 
n-type semiconductor is built by doping intrinsic silicon with a group _______ element - 
CORRECT ANSWER - V
Exam (elaborations)
EDA / VLSI Concepts UPDATED ACTUAL Exam Questions and CORRECT Answers
EDA / VLSI Concepts UPDATED ACTUAL 
Exam Questions and CORRECT Answers 
Net List - CORRECT ANSWER - List of properties and statistics usually for connection of 
cells. There are different levels of net-list. ex: Gate level net-list 
Standard Cell - CORRECT ANSWER 
standalone gates. - Cells are a combination of logic gates or 
Standard Cell Library - CORRECT ANSWER - A collection of all possible cells used in 
the design of the chips entirety. The standard cells are created and p...
Exam (elaborations)
VLSI Exam 1 UPDATED ACTUAL Exam Questions and CORRECT Answers
VLSI Exam 1 UPDATED ACTUAL Exam 
Questions and CORRECT Answers 
What is the impact of reducing Vdd of a CMOS inverter? - CORRECT ANSWER 
Reduces noise margin 
2. Reduces drain current which will drop propagation delay 
3. Rise and fall time of output increases 
What are the attributes of the subthreshold current in MOSFET? - CORRECT ANSWER 
1. Subthreshold current increases with increase in temp 
2. DIBL (Drain Induced Barrier Lowering) reduces the barrier thus subthreshold curre...
Exam (elaborations)
VLSI exam practices questions with 100% updated answers.get a pass on your first trial!!
What are the three main design objectives in VLSI, related to Global Interconnect - correct answers️️1. Propagation delay: With smaller feature sizes, the number of interconnects increased exponentially. This means more delay 
2. Power Consumption: Interconnect coupling capacitance dominates the gate load. A majority of the transient power is dissipated on these capacitive lines. 
3. Signal Noise: Coupling capacitance degrades signal integrity. Creates delay uncertainty causing synchronizat...
Exam (elaborations)
VLSI Final Exam Questions with Correct Answers Latest Version 2025
VLSI Final Exam Questions with Correct Answers Latest Version 2025 
What does the mobility in MOS mean and what is the general relation between NMOS and PMOS mobility? - Answers Mobility means how fast the electrons/holes move in a semiconductor 
What is the relation between MOS gate's 
i) length & resistance? 
ii) width and resistance? - Answers i) when length increases, resistance of the channel increases. 
ii) when width increases, resistance of the channel decreases. 
Which materials do...