EDA / VLSI Concepts UPDATED ACTUAL
Exam Questions and CORRECT Answers
Net List - CORRECT ANSWER - List of properties and statistics usually for connection of
cells. There are different levels of net-list. ex: Gate level net-list
Standard Cell - CORRECT ANSWER - Cells are a combination of logic gates or
standalone gates.
Standard Cell Library - CORRECT ANSWER - A collection of all possible cells used in
the design of the chips entirety. The standard cells are created and provided by the foundry in
order to make place and route easier.
VDD and VSS - CORRECT ANSWER - VDD means the ground and VSS means the
voltage source. VSS and VDD can also be written as VCC and GND respectively.
Power and Ground Lines - CORRECT ANSWER - Power and ground lines are VSS and
VDD. The lines are alternating and allow for set orientation of cells in a uniform pattern.
DRC - CORRECT ANSWER - Design Rule Check: A check of geometry, orientation, and
spacing of wires and vias.
LVS - CORRECT ANSWER - Layout vs Schematic: A check of connectivity of the entire
system.
VIA - CORRECT ANSWER - Via connections are alloy metals : usually varying
depending on metal properties. Used to connect different metal layers together.
Fixing Violations (ECO) - CORRECT ANSWER - When there are still violations after
doing some automatic rerouting, there are issues surrounding wire connectivity or geometry that
can only be fixed by humans. Using the place and route tools the engineer can easily manually
, manipulate the wires to resolve the violations presented. We call this an (Engineer Change
Order)
Global Routing - CORRECT ANSWER - (Tile routing) The program runs algorithms that
roughly route the path the wire should take to make the connection through a imaginary
partitioned tile structure.
[Common Methods / Algorithms]
Sequential Global (Rip and Replace)
Concurrent Global Routing (0-1)
Steiner Trees (Shortest possible path via Steiner nodes)
Detailed Routing - CORRECT ANSWER - Using the global route given the placer tool
can now use its algorithm to place physical wires to represent the path taken. Paths can extend
through multiple metal layers and all of them are now represented along with their vias.
Congestion Map - CORRECT ANSWER - These maps are very similar to heat maps. The
more wires there are the darker the color (ranges from blue to red). To more simply put it, this
map shows wire density. It can be used to show how many possible connections are left in a
certain region and whether or not one should reroute or place wires elsewhere.
APR - CORRECT ANSWER - Auto Place and Route (Back-End)
CMOS / MOSFET - CORRECT ANSWER - Complementary Metal Oxide Semiconductor
/ Metal Oxide Semiconductor Field Effect Transistor
In its most simple form: P-type + N-type
PMOS (P-type) - CORRECT ANSWER - A type of logic gate that reacts to a digital signal
G = 0 when closed and G = 1 when open.p
NMOS (N-type) - CORRECT ANSWER - A type of logic gate that reacts to a digital
signal G = 1 when closed and G = 0 when open.n
Exam Questions and CORRECT Answers
Net List - CORRECT ANSWER - List of properties and statistics usually for connection of
cells. There are different levels of net-list. ex: Gate level net-list
Standard Cell - CORRECT ANSWER - Cells are a combination of logic gates or
standalone gates.
Standard Cell Library - CORRECT ANSWER - A collection of all possible cells used in
the design of the chips entirety. The standard cells are created and provided by the foundry in
order to make place and route easier.
VDD and VSS - CORRECT ANSWER - VDD means the ground and VSS means the
voltage source. VSS and VDD can also be written as VCC and GND respectively.
Power and Ground Lines - CORRECT ANSWER - Power and ground lines are VSS and
VDD. The lines are alternating and allow for set orientation of cells in a uniform pattern.
DRC - CORRECT ANSWER - Design Rule Check: A check of geometry, orientation, and
spacing of wires and vias.
LVS - CORRECT ANSWER - Layout vs Schematic: A check of connectivity of the entire
system.
VIA - CORRECT ANSWER - Via connections are alloy metals : usually varying
depending on metal properties. Used to connect different metal layers together.
Fixing Violations (ECO) - CORRECT ANSWER - When there are still violations after
doing some automatic rerouting, there are issues surrounding wire connectivity or geometry that
can only be fixed by humans. Using the place and route tools the engineer can easily manually
, manipulate the wires to resolve the violations presented. We call this an (Engineer Change
Order)
Global Routing - CORRECT ANSWER - (Tile routing) The program runs algorithms that
roughly route the path the wire should take to make the connection through a imaginary
partitioned tile structure.
[Common Methods / Algorithms]
Sequential Global (Rip and Replace)
Concurrent Global Routing (0-1)
Steiner Trees (Shortest possible path via Steiner nodes)
Detailed Routing - CORRECT ANSWER - Using the global route given the placer tool
can now use its algorithm to place physical wires to represent the path taken. Paths can extend
through multiple metal layers and all of them are now represented along with their vias.
Congestion Map - CORRECT ANSWER - These maps are very similar to heat maps. The
more wires there are the darker the color (ranges from blue to red). To more simply put it, this
map shows wire density. It can be used to show how many possible connections are left in a
certain region and whether or not one should reroute or place wires elsewhere.
APR - CORRECT ANSWER - Auto Place and Route (Back-End)
CMOS / MOSFET - CORRECT ANSWER - Complementary Metal Oxide Semiconductor
/ Metal Oxide Semiconductor Field Effect Transistor
In its most simple form: P-type + N-type
PMOS (P-type) - CORRECT ANSWER - A type of logic gate that reacts to a digital signal
G = 0 when closed and G = 1 when open.p
NMOS (N-type) - CORRECT ANSWER - A type of logic gate that reacts to a digital
signal G = 1 when closed and G = 0 when open.n
