Questions and CORRECT Answers
functional test - CORRECT ANSWER - development errors :
correct functionality of the modules is tested in a functional test; a high
coverage of the fault is targeted, leading to a long test process
structural test - CORRECT ANSWER - physical or manufacturing defects:
the presence of all signal lines, and their ability to carry 0 and 1s is
checked in a structural test
Verification - CORRECT ANSWER - Predictive analysis to ensure that the synthesized
design, when manufactured, will perform the given I/O function.
- Verifies correctness of design.
- Performed by simulation, hardware emulation, or formal methods.
Test - CORRECT ANSWER - A manufacturing step that ensures that the physical device,
manufactured from the synthesized design, has no manufacturing
defect.
- Checks the correctness of manufactured hardware.
- Two-part process:
1. during the design of the system, test structures are included on-chip, and
software simulation enable deducting test vectors
2. after the chip is fabricated, electrical tests are applied to the hardware
The rule of Ten - CORRECT ANSWER - The cost of discovering a defective chip
increases by an order of magnitude at each successive level of integration, from die/package,
board
, and system.
issues of testing - CORRECT ANSWER - scales
complexity
issues of testing : scales - CORRECT ANSWER - the silicon chip delivered back from
fabrication has no dimensions
in match with human scale (e.g. Sony Cell processor, 2006)
- it is tiny: 221mm2 in a 65nm technology
- it has a huge number of transistors: 234e6
- it runs fast: 4.6GHz
issues of testing : dimensions - CORRECT ANSWER - the chip is formed of numerous
functional blocks
- datapath, memory, control logic, etc.
- each of these blocks are conceived by different groups, using various
development methods
Roles of testing - CORRECT ANSWER - Detection Determination whether or not the
device under test
(DUT) has any fault
- identification of process flaw
- detection of chips that must not be sold to customers
• Diagnosis Location and identification of a specific fault that is
present on DUT
• Failure mode analysis (FMA) Determination of manufacturing
process errors that may have caused defects on the DUT
- used in all stages of test in order to improve the manufacturing process
and the number of fault-free chips