VLSI Exam 1 UPDATED Exam Questions and CORRECT Answers

VLSI Exam 1 UPDATED Exam Questions
and CORRECT Answers
When two 2Y/4Y transistors are connected in series its equivalent resistance can be calculated
from a single transistor with size: - CORRECT ANSWER - 4Y/4Y
*cannot reduce*


When two 2Y/4Y transistors are connected in parallel its equivalent resistance can be calculated
from a single transistor with size: - CORRECT ANSWER - 2Y/8Y



The starting material of the n-well process is: - CORRECT ANSWER - lightly doped p-
type substrate


The gate of a PMOS is connected to logic 1 and the source terminal is connected to VDD, at the
drain we get: - CORRECT ANSWER - Hi-Z


The number of transistors needed to realize a 4 input CMOS NOR gate is: - CORRECT
ANSWER - 8 b/c (2n)


Which of the following is NOT used as a mask in CMOS processing? - CORRECT
ANSWER - metal



Minimum number of pins needed in a 16x1 multiplexer chip is: - CORRECT ANSWER -
16 input lines
1 output line
1 vdd
1 gnd
4 select lines (2^(4)=16)
23 Total

, Metal depositions are accomplished by: - CORRECT ANSWER - -evaporation
-sputtering
-CVD(chemical vapor deposition)
-electroplating


In 90nm technology the value of Y= - CORRECT ANSWER - 45nm
b/c 2Y=90nm


Reducing the channel length ________ the transistor operating speed. - CORRECT
ANSWER - increases


In a single poly 3-metal process, excluding the diffusion area, the number of layers available for
interconnection is: - CORRECT ANSWER -4



If the width of a transistor increases, the current will: - CORRECT ANSWER - increase



If the length of a transistor increases the channel resistance will: - CORRECT ANSWER -
increase


If the supply voltage of a chip increases, the maximum transistor current will: - CORRECT
ANSWER - increase



Fabless companies: - CORRECT ANSWER - Qualcomm
Broadcom
Nvidia
Apple
AMD
HiSilicon
Xilinx