VLSI Testing and Design for Testability
UPDATED ACTUAL Exam Questions and
CORRECT Answers
Logic Verification - CORRECT ANSWER - Ensures chip performs intended functions
accurately.
Silicon Debug - CORRECT ANSWER - Tests initial chips post-fabrication for errors.
Manufacturing Test - CORRECT ANSWER - Tests every chip before delivery to ensure
quality.
Fault Models - CORRECT ANSWER - Models describing how faults impact circuits.
Observability - CORRECT ANSWER - Ability to observe internal states of a circuit.
Controllability - CORRECT ANSWER - Ability to control inputs to a circuit.
Design for Test - CORRECT ANSWER - Techniques to make testing easier and more
effective.
Scan Design - CORRECT ANSWER - Technique for improving observability and
controllability.
BIST - CORRECT ANSWER - Built-In Self-Test; self-testing capability in chips.
JTAG - CORRECT ANSWER - Joint Test Action Group; standard for testing.
, Boundary Scan - CORRECT ANSWER - Technique for testing interconnections between
chips.
Path Sensitizing - CORRECT ANSWER - Method to ensure test patterns activate faults.
Test Patterns - CORRECT ANSWER - Specific sequences of inputs used for testing.
Shmoo Plots - CORRECT ANSWER - Graphs used to diagnose electrical failures.
Crosstalk - CORRECT ANSWER - Unwanted transfer of signals between circuit paths.
Dynamic Nodes - CORRECT ANSWER - Nodes affected by leakage and charge sharing.
Logic Bugs - CORRECT ANSWER - Errors in logic design causing incorrect outputs.
Electrical Failures - CORRECT ANSWER - Malfunctions due to environmental
conditions.
Test Vectors - CORRECT ANSWER - Specific input combinations used in testing.
Yield - CORRECT ANSWER - Percentage of functional chips from a manufacturing
batch.
Test Bench - CORRECT ANSWER - Environment for testing HDL simulations.
Corner Cases - CORRECT ANSWER - Extreme input conditions used to test limits.
UPDATED ACTUAL Exam Questions and
CORRECT Answers
Logic Verification - CORRECT ANSWER - Ensures chip performs intended functions
accurately.
Silicon Debug - CORRECT ANSWER - Tests initial chips post-fabrication for errors.
Manufacturing Test - CORRECT ANSWER - Tests every chip before delivery to ensure
quality.
Fault Models - CORRECT ANSWER - Models describing how faults impact circuits.
Observability - CORRECT ANSWER - Ability to observe internal states of a circuit.
Controllability - CORRECT ANSWER - Ability to control inputs to a circuit.
Design for Test - CORRECT ANSWER - Techniques to make testing easier and more
effective.
Scan Design - CORRECT ANSWER - Technique for improving observability and
controllability.
BIST - CORRECT ANSWER - Built-In Self-Test; self-testing capability in chips.
JTAG - CORRECT ANSWER - Joint Test Action Group; standard for testing.
, Boundary Scan - CORRECT ANSWER - Technique for testing interconnections between
chips.
Path Sensitizing - CORRECT ANSWER - Method to ensure test patterns activate faults.
Test Patterns - CORRECT ANSWER - Specific sequences of inputs used for testing.
Shmoo Plots - CORRECT ANSWER - Graphs used to diagnose electrical failures.
Crosstalk - CORRECT ANSWER - Unwanted transfer of signals between circuit paths.
Dynamic Nodes - CORRECT ANSWER - Nodes affected by leakage and charge sharing.
Logic Bugs - CORRECT ANSWER - Errors in logic design causing incorrect outputs.
Electrical Failures - CORRECT ANSWER - Malfunctions due to environmental
conditions.
Test Vectors - CORRECT ANSWER - Specific input combinations used in testing.
Yield - CORRECT ANSWER - Percentage of functional chips from a manufacturing
batch.
Test Bench - CORRECT ANSWER - Environment for testing HDL simulations.
Corner Cases - CORRECT ANSWER - Extreme input conditions used to test limits.
