Engr 325 Study guides, Class notes & Summaries

ENGR 325 HOMEWORK 7 KEY FALL 2020. In this exercise we look at memory locality properties of matrix computation. The following code is written in C, where elements within the same row are stored contiguously. Assume each word is a 32-bit integer. (P&H 5.1, §5.1) for (I=0; I<8; I++) for (J=0; J<8000; J++) A[I][J]=B[I][0]+A[J][I]; a. How many 32-bit integers can be stored in a 16-byte cache block? b. References to which variables exhibit temporal locality? c. References to which...

(5) Aside from the smart cell phones used by a billion people, list and describe four other types of computers. (P&H 1.1, §1.1) SOLUTION:  Desktop PC – relatively powerful, single user, personal machine  Server – more powerful, large workloads or many small tasks, reliable  Supercomputer – often tailor-mode for a specific task or set of tasks  Embedded computers – computers in automobiles, white goods, planes, printers, etc.  Tablet – positioned between smart pho...

(5) Assume that the logic blocks needed to implement a processor’s datapath have the latencies shown in the table below. These problems refer to the datapath element Shift-Left-2. (P&H 4.4, §4.3) Block Latency (ps) I-Mem 200 Add 70 Mux 20 ALU 90 Regs 90 D-Mem 250 Sign-Extend 15 Shift-Left-2 10 a. Which kinds of instructions require this resource? b. For which kinds of instructions (if any) is this resource on the critical path? SOLUTION:

(5) Mean Time Between Failures (MTBF), Mean Time To Replacement (MTTR), and Mean Time To Failure (MTTF) are useful metrics for evaluating the reliability and availability of a storage resource. Explore these concepts by answering the questions about devices with the following metrics. (P&H 5.8, §5.5) MTTF MTTR a. 3 Years 1 Day b. 7 Years 3 Days a. Calculate the MTBF for each of the devices in the table. b. Calculate the availability for each of the devices in the table. c. What happens...

ENGR 325 HOMEWORK 7. 1. (5) In this exercise we look at memory locality properties of matrix computation. The following code is written in C, where elements within the same row are stored contiguously. Assume each word is a 32-bit integer. (P&H 5.1, §5.1) for (I=0; I<8; I++) for (J=0; J<8000; J++) A[I][J]=B[I][0]+A[J][I]; a. How many 32-bit integers can be stored in a 16-byte cache block? b. References to which variables exhibit temporal locality? c. References to which variables ...

(5) In this exercise we look at memory locality properties of matrix computation. The following code is written in C, where elements within the same row are stored contiguously. Assume each word is a 32-bit integer. (P&H 5.1, §5.1) for (I=0; I<8; I++) for (J=0; J<8000; J++) A[I][J]=B[I][0]+A[J][I]; a. How many 32-bit integers can be stored in a 16-byte cache block? b. References to which variables exhibit temporal locality? c. References to which variables exhibit spatial locality...

ENGR 325 HOMEWORK 7 KEY. 1. (5) In this exercise we look at memory locality properties of matrix computation. The following code is written in C, where elements within the same row are stored contiguously. Assume each word is a 32-bit integer. (P&H 5.1, §5.1) for (I=0; I<8; I++) for (J=0; J<8000; J++) A[I][J]=B[I][0]+A[J][I]; a. How many 32-bit integers can be stored in a 16-byte cache block? b. References to which variables exhibit temporal locality? c. References to which variab...

. (5) For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, and h are given and could be considered 32-bit integers as declared in a C program. Use a minimal number of MIPS instructions. (P&H 2.1, §2.2) f = g + (h – 5); SOLUTION: Since f, g, and h are declared registers, the corresponding assembly code is: addi f, h, -5 # f = h - 5 add f, f, g # f = f + g 2. (5) For the following MIPS assembly instructions, what is a corresponding...

5) Recall that we have two write policies and write allocation policies, and their combination can be implemented either in L1 or L2 cache. Assume the following choice for L1 and L2 caches: L1 L2 Write-through, non-write allocate Write-back, write allocate Describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block. (P&H 5.4, §5.3, 5.8) SOLUTION: When an L1 write miss occurs, a cache block is not allocated in L1 f...