12/15/25, 9:49 PM ITE 221 - PC Hardware & O/C Architecture - Exam 2
ITE 221 - PC Hardware & O/S Architecture – Exam 2
Northern Virginia Community College NEWEST VERSION
WITH COMPLETE QUESTIONS AND CORRECT DETAILED
ANSWERS\ACTUAL EXAM ITE 221 EXAM 2026-2027
\LATEST VERSION
L1 or level one A(n) cache is generally implemented on the same chip as the
CPU.
A(n) is an area of fast memory where data held in a storage
cache
device is prefetched
in anticipation of future requests for the data.
A cache controller is a hardware device that initiates a(n)when it
cache swap
detects a cache
miss.
The _____________________________ transmits command,
timing, and status signals between devices in a
control bus computer system and carries interrupts, command responses,
status codes, and similar messages.
The _____________________________ is a special-purpose
stack pointer
register that always points to the next empty address in
the stack.
The set of register values stored in the stack while processing an
machine state
interrupt is also called the ___________ _.
A(n) ____________________________ is a program stored in a
interrupt handler
separate part of primary storage to process a
specific interrupt.
During interrupt processing, register values of a suspended
stack
process are held on the
_____.
/ 1/1
4
, 12/15/25, 9:49 PM ITE 221 - PC Hardware & O/C Architecture - Exam 2
The has a much higher data transfer rate than the system bus
memory bus
because of its
shorter length, higher clock rate, and large number of parallel
communication lines.
cache controller A(n) is a special-purpose processor dedicated to managing
cache content.
The transmits a memory address when primary storage is the
address bus
sending or
receiving device.
The CPU and bus normally view and storage device as a(n) ,
linear address space
ignoring the device's
physical storage organization.
logical accesses Part of a device controller's function is to translate into physical
accesses.
A(n) controller assumes the role of bus master for all transfers
DMA between memory
and other storage or I/O devices, leaving the CPU free
to execute computation and data movement
instructions.
channel A(n) is a high-capacity device controller used in mainframe
computers.
When a read operation accesses data already contained in the
cache hit
cache, it's called a(n)
_____.
The defines the format, content, and timing of data, memory
bus protocol
addresses, and
control messages sent across the bus.
In _ architecture, multiple CPUs and cache memory are
multicore
embedded on a single
chip.
The term describes methods of increasing processing and other
scaling up
computer
system power by using larger and more powerful computers.
Storage Examples of a(n)bus include SATA and SCSI.
The secondary storage devices for a mainframe could
TRUE
include many different types of storage devices, such as
magnetic disks, optical discs, and magnetic tape drives.
TRUE MPEG standards address recording and encoding for both audio
and video data.
The memory bus has a much higher data transfer rate
TRUE than the system bus because of its shorter length,
higher clock rate, and (in most computers) large
/ 2/1
4
ITE 221 - PC Hardware & O/S Architecture – Exam 2
Northern Virginia Community College NEWEST VERSION
WITH COMPLETE QUESTIONS AND CORRECT DETAILED
ANSWERS\ACTUAL EXAM ITE 221 EXAM 2026-2027
\LATEST VERSION
L1 or level one A(n) cache is generally implemented on the same chip as the
CPU.
A(n) is an area of fast memory where data held in a storage
cache
device is prefetched
in anticipation of future requests for the data.
A cache controller is a hardware device that initiates a(n)when it
cache swap
detects a cache
miss.
The _____________________________ transmits command,
timing, and status signals between devices in a
control bus computer system and carries interrupts, command responses,
status codes, and similar messages.
The _____________________________ is a special-purpose
stack pointer
register that always points to the next empty address in
the stack.
The set of register values stored in the stack while processing an
machine state
interrupt is also called the ___________ _.
A(n) ____________________________ is a program stored in a
interrupt handler
separate part of primary storage to process a
specific interrupt.
During interrupt processing, register values of a suspended
stack
process are held on the
_____.
/ 1/1
4
, 12/15/25, 9:49 PM ITE 221 - PC Hardware & O/C Architecture - Exam 2
The has a much higher data transfer rate than the system bus
memory bus
because of its
shorter length, higher clock rate, and large number of parallel
communication lines.
cache controller A(n) is a special-purpose processor dedicated to managing
cache content.
The transmits a memory address when primary storage is the
address bus
sending or
receiving device.
The CPU and bus normally view and storage device as a(n) ,
linear address space
ignoring the device's
physical storage organization.
logical accesses Part of a device controller's function is to translate into physical
accesses.
A(n) controller assumes the role of bus master for all transfers
DMA between memory
and other storage or I/O devices, leaving the CPU free
to execute computation and data movement
instructions.
channel A(n) is a high-capacity device controller used in mainframe
computers.
When a read operation accesses data already contained in the
cache hit
cache, it's called a(n)
_____.
The defines the format, content, and timing of data, memory
bus protocol
addresses, and
control messages sent across the bus.
In _ architecture, multiple CPUs and cache memory are
multicore
embedded on a single
chip.
The term describes methods of increasing processing and other
scaling up
computer
system power by using larger and more powerful computers.
Storage Examples of a(n)bus include SATA and SCSI.
The secondary storage devices for a mainframe could
TRUE
include many different types of storage devices, such as
magnetic disks, optical discs, and magnetic tape drives.
TRUE MPEG standards address recording and encoding for both audio
and video data.
The memory bus has a much higher data transfer rate
TRUE than the system bus because of its shorter length,
higher clock rate, and (in most computers) large
/ 2/1
4
