CSE 230 Final Question and answers
100% correct 2025/2026
1. Select the hardware that is active during the Data Memory
Memory Access stage of the instruction
cycle:
Data Memory
Program Counter
Instruction
Memory Control
Unit Register File
ALU
2. Stages of Instruction Cycle
Fetc
h
Decod
e
Execut
e
Stor
e
3. Select the hardware that is active during the of an N-stage
Fetch Stage of the instruction cycle: pipelined
processor?
Register File
ALU N
Data Memory /
Program Counter 2
Instruction
Memory Control N
Unit N
*
4. What is the maximum speedup (upper limit) N
1/
38
,4 Program Counter
Instruction Memory
N
2/
38
, CSE 230 Final
Study online at https://quizlet.com/_cs9cip
5. Which of the following are true about single In a single cycle
cycle vs. pipelined processor designs? design, a single
(Select all that apply). instruction is ex-
ecuting in the
processor
Pipelined processors have decreased throughput com- during any
single clock cy-
pared to single-cycle cle.
designs.
The clock rate of single-cycle processors can be higher In a pipelined
design, the
than that of pipelined designs. processor components
are fully utilized, but by
In a single cycle design, a single instruction is
ditter- ent
execut- ing in the processor during any
instructions.
single clock cycle.
In a pipelined design, the processor
components are fully utilized, but by different
instructions.
Increased throughput.
6. The speedup of a pipelined processor is due
to the: Increased instruction count.
Reduced latency of executing each instruction.
Reduced complexity of processor hardware.
Increased throughput.
7. Which of the following must be added to a single-cycle Modified
Registers for si-
processor in order to implement a pipelined design?
3/
38
, (Select all that apply) multaneous read/write.
Modified Registers for simultaneous read/write. Hazard Detection & Mitiga-
tion Hardware
Hazard Detection & Mitigation Hardware
Pipeline Registers
Additional RAM
4/
38
100% correct 2025/2026
1. Select the hardware that is active during the Data Memory
Memory Access stage of the instruction
cycle:
Data Memory
Program Counter
Instruction
Memory Control
Unit Register File
ALU
2. Stages of Instruction Cycle
Fetc
h
Decod
e
Execut
e
Stor
e
3. Select the hardware that is active during the of an N-stage
Fetch Stage of the instruction cycle: pipelined
processor?
Register File
ALU N
Data Memory /
Program Counter 2
Instruction
Memory Control N
Unit N
*
4. What is the maximum speedup (upper limit) N
1/
38
,4 Program Counter
Instruction Memory
N
2/
38
, CSE 230 Final
Study online at https://quizlet.com/_cs9cip
5. Which of the following are true about single In a single cycle
cycle vs. pipelined processor designs? design, a single
(Select all that apply). instruction is ex-
ecuting in the
processor
Pipelined processors have decreased throughput com- during any
single clock cy-
pared to single-cycle cle.
designs.
The clock rate of single-cycle processors can be higher In a pipelined
design, the
than that of pipelined designs. processor components
are fully utilized, but by
In a single cycle design, a single instruction is
ditter- ent
execut- ing in the processor during any
instructions.
single clock cycle.
In a pipelined design, the processor
components are fully utilized, but by different
instructions.
Increased throughput.
6. The speedup of a pipelined processor is due
to the: Increased instruction count.
Reduced latency of executing each instruction.
Reduced complexity of processor hardware.
Increased throughput.
7. Which of the following must be added to a single-cycle Modified
Registers for si-
processor in order to implement a pipelined design?
3/
38
, (Select all that apply) multaneous read/write.
Modified Registers for simultaneous read/write. Hazard Detection & Mitiga-
tion Hardware
Hazard Detection & Mitigation Hardware
Pipeline Registers
Additional RAM
4/
38
