CECS 341 FINAL QUESTIONS &
ANSWERS (RATED A+)
Calculate the time required to fetch, decode, and execute the ADD instruction. -
ANSWERTime for ADD = max{Read I-Mem, Increment PC} + max{Read Rs, Read
Rt} + Calculate sum (ALU) + Write result to Rd (Mux, RF)
CPIAVG weighted average formula? - ANSWERCPIAVG = (FC1 * CPIC1) + (FC2 *
CPIC2) + (FC3 * CPIC3) + (FC4 * CPIC4)
[FC1, FC2, etc. are the frequency in the program. should be a percentage)
Sequence 2: IC = 4 + 1 + 1 = 6
-Clock Cycles= 4×1 + 1×2 + 1×3= 9
- Avg. CPI = 9/6 = 1.5
Consider the MIPS assembly language program given below.
I1: lw $s0, 0($t0)
I2: lw $s1, 4($t0)
I3: add $s2, $zero, $zero
I4: add $s3, $zero, $zero
I5: add $s4, $zero, $zero
Assumption 1: The MIPS pipelined processor uses a single memory to store both
instructionsand data.Assumption 2: Data read and write take precedence over
instruction fetch.
What type of hazard does this pipelined processor have? - ANSWERResource
(structural) hazard due to a single memory used to store both instructions and data
Consider the MIPS assembly language program given below.
I1: lw $s0, 0($t0)
I2: lw $s1, 4($t0)
I3: add $s2, $zero, $zero
I4: add $s3, $zero, $zero
I5: add $s4, $zero, $zero
Space metric - ANSWERAmount of memory required by a program for instructions
and data
aka. Memory footprint.
Not necessarily correlated to the program execution time
What are four time metrics? - ANSWERInstruction Latency, Execution Time (ET),
Throughput, Processor Performance
, Instruction Latency - ANSWERTime required to complete a single instruction.
Includes fetch, decode, and execution of instruction.
Usually measured in seconds.
Execution Time (ET) - ANSWERTime required to complete a program or a code
segment.
Includes fetch, decode, and execution of all instructions.
Usually measured in seconds or seconds per instruction.
Assumption 1: The MIPS pipelined processor uses a single memory to store both
instructionsand data.Assumption 2: Data read and write take precedence over
instruction fetch.
Calculate the total number of clock cycles to execute the given program on this
processor. - ANSWER11 clock cycles.
As can be seen in the figure below, in clock cycle #4, I1 is being processed in the
MEMstage of the pipeline and is reading from data memory. Given that there is only
one memoryavailable, and since data read takes precedence over an instruction
fetch, I4 cannot befetched from memory in this clock cycle. Therefore, I4 is fetched in
clock cycle #6 afterhaving been stalled two clock cycles.
We have a memory system with following specification:
- Main memory size = 1M byte
- Cache size = 128 bytes
- Block size = 8 bytes
- Two-way Set-associative cache (w = 2).
Determine the number of blocks in main memory - ANSWER# blocks in MM = Main
memory size / Block size
# blocks in MM = 1M byte / 8 bytes = 2^^3 = 2^17 = 131072 blocks.
We have a memory system with following specification:
- Main memory size = 1M byte
- Cache size = 128 bytes
- Block size = 8 bytes
- Two-way Set-associative cache (w = 2).
Determine the number of blocks in the cache. - ANSWER# blocks in cache = Cache
size / Block size
# blocks in cache = 128 bytes / 8 bytes = 16 blocks
We have a memory system with following specification:
- Main memory size = 1M byte
- Cache size = 128 bytes
- Block size = 8 bytes
- Two-way Set-associative cache (w = 2).
Determine the number of sets in the cache. - ANSWER# sets in cache = # blocks in
cache / # blocks in each set
# blocks in cache = 16 blocks
ANSWERS (RATED A+)
Calculate the time required to fetch, decode, and execute the ADD instruction. -
ANSWERTime for ADD = max{Read I-Mem, Increment PC} + max{Read Rs, Read
Rt} + Calculate sum (ALU) + Write result to Rd (Mux, RF)
CPIAVG weighted average formula? - ANSWERCPIAVG = (FC1 * CPIC1) + (FC2 *
CPIC2) + (FC3 * CPIC3) + (FC4 * CPIC4)
[FC1, FC2, etc. are the frequency in the program. should be a percentage)
Sequence 2: IC = 4 + 1 + 1 = 6
-Clock Cycles= 4×1 + 1×2 + 1×3= 9
- Avg. CPI = 9/6 = 1.5
Consider the MIPS assembly language program given below.
I1: lw $s0, 0($t0)
I2: lw $s1, 4($t0)
I3: add $s2, $zero, $zero
I4: add $s3, $zero, $zero
I5: add $s4, $zero, $zero
Assumption 1: The MIPS pipelined processor uses a single memory to store both
instructionsand data.Assumption 2: Data read and write take precedence over
instruction fetch.
What type of hazard does this pipelined processor have? - ANSWERResource
(structural) hazard due to a single memory used to store both instructions and data
Consider the MIPS assembly language program given below.
I1: lw $s0, 0($t0)
I2: lw $s1, 4($t0)
I3: add $s2, $zero, $zero
I4: add $s3, $zero, $zero
I5: add $s4, $zero, $zero
Space metric - ANSWERAmount of memory required by a program for instructions
and data
aka. Memory footprint.
Not necessarily correlated to the program execution time
What are four time metrics? - ANSWERInstruction Latency, Execution Time (ET),
Throughput, Processor Performance
, Instruction Latency - ANSWERTime required to complete a single instruction.
Includes fetch, decode, and execution of instruction.
Usually measured in seconds.
Execution Time (ET) - ANSWERTime required to complete a program or a code
segment.
Includes fetch, decode, and execution of all instructions.
Usually measured in seconds or seconds per instruction.
Assumption 1: The MIPS pipelined processor uses a single memory to store both
instructionsand data.Assumption 2: Data read and write take precedence over
instruction fetch.
Calculate the total number of clock cycles to execute the given program on this
processor. - ANSWER11 clock cycles.
As can be seen in the figure below, in clock cycle #4, I1 is being processed in the
MEMstage of the pipeline and is reading from data memory. Given that there is only
one memoryavailable, and since data read takes precedence over an instruction
fetch, I4 cannot befetched from memory in this clock cycle. Therefore, I4 is fetched in
clock cycle #6 afterhaving been stalled two clock cycles.
We have a memory system with following specification:
- Main memory size = 1M byte
- Cache size = 128 bytes
- Block size = 8 bytes
- Two-way Set-associative cache (w = 2).
Determine the number of blocks in main memory - ANSWER# blocks in MM = Main
memory size / Block size
# blocks in MM = 1M byte / 8 bytes = 2^^3 = 2^17 = 131072 blocks.
We have a memory system with following specification:
- Main memory size = 1M byte
- Cache size = 128 bytes
- Block size = 8 bytes
- Two-way Set-associative cache (w = 2).
Determine the number of blocks in the cache. - ANSWER# blocks in cache = Cache
size / Block size
# blocks in cache = 128 bytes / 8 bytes = 16 blocks
We have a memory system with following specification:
- Main memory size = 1M byte
- Cache size = 128 bytes
- Block size = 8 bytes
- Two-way Set-associative cache (w = 2).
Determine the number of sets in the cache. - ANSWER# sets in cache = # blocks in
cache / # blocks in each set
# blocks in cache = 16 blocks
