WGU C952 Chapter 5 Knowledge test Exam Toolkit
Questions and Verified Marking Scheme 2024/2025
Instruction-level parallelism (ilp) - correct answer the parallelism among instructions.
Multiple issue - correct answer a scheme whereby multiple instructions are launched in
one clock cycle
Static multiple issue - correct answer an approach to implementing a multiple-issue
processor where many decisions are made by the compiler before execution
Dynamic multiple issue - correct answer an approach to implementing a multiple-issue
processor where many decisions are made during execution by the processor
Issue slots - correct answer the positions from which instructions could issue in a given
clock cycle
Correspond to positions at the starting blocks for a sprint
Speculation - correct answer an approach whereby the compiler or processor guesses
the outcome of an instruction to remove it as a dependence in executing other
instructions
Issue packet - correct answer the set of instructions that issues together in one clock
cycle; determined statically by the compiler and dynamically by the processor
Very long instruction word (vliw) - correct answer a style of instruction set architecture
that launches many operations that are defined to be independent in a single wide
instruction typically with many separate opcode fields
, Use latency - correct answer number of clock cycled between a load instruction and an
instruction that can use the result of the load without stalling the pipeline
Register renaming - correct answer done by the compiler or hardware to remove
antidependences
Antidependence (name dependence) - correct answer an ordering forced by the reuse
of a name
Typically a register (rather than true dependent that carries a value b.t two instructions)
Superscalar - correct answer an advanced pipelining technique that enables the
processor to execute more than one instruction per clock cycle by selecting them during
execution
Commit unit - correct answer the unit in a dynamic or out-of-order execution pipeline
that decides when it is safe to release the result of an operation to programmer-visible
registers and memory
Reservation station - correct answer a buffer within a functional unit that holds the
operands and the operation
Reorder buffer - correct answer the buffer that holds results in a dynamically scheduled
processor until it is safe to store the results to memory or a register.
Out-of-order execution - correct answer a situation in pipelined execution when an
instruction blocked from executing does not cause the following instructions to wait
In-order commit - correct answer a commit in which the results of pipelined execution
are written to the programmer visible state in the same order that instructions are
fetched
Questions and Verified Marking Scheme 2024/2025
Instruction-level parallelism (ilp) - correct answer the parallelism among instructions.
Multiple issue - correct answer a scheme whereby multiple instructions are launched in
one clock cycle
Static multiple issue - correct answer an approach to implementing a multiple-issue
processor where many decisions are made by the compiler before execution
Dynamic multiple issue - correct answer an approach to implementing a multiple-issue
processor where many decisions are made during execution by the processor
Issue slots - correct answer the positions from which instructions could issue in a given
clock cycle
Correspond to positions at the starting blocks for a sprint
Speculation - correct answer an approach whereby the compiler or processor guesses
the outcome of an instruction to remove it as a dependence in executing other
instructions
Issue packet - correct answer the set of instructions that issues together in one clock
cycle; determined statically by the compiler and dynamically by the processor
Very long instruction word (vliw) - correct answer a style of instruction set architecture
that launches many operations that are defined to be independent in a single wide
instruction typically with many separate opcode fields
, Use latency - correct answer number of clock cycled between a load instruction and an
instruction that can use the result of the load without stalling the pipeline
Register renaming - correct answer done by the compiler or hardware to remove
antidependences
Antidependence (name dependence) - correct answer an ordering forced by the reuse
of a name
Typically a register (rather than true dependent that carries a value b.t two instructions)
Superscalar - correct answer an advanced pipelining technique that enables the
processor to execute more than one instruction per clock cycle by selecting them during
execution
Commit unit - correct answer the unit in a dynamic or out-of-order execution pipeline
that decides when it is safe to release the result of an operation to programmer-visible
registers and memory
Reservation station - correct answer a buffer within a functional unit that holds the
operands and the operation
Reorder buffer - correct answer the buffer that holds results in a dynamically scheduled
processor until it is safe to store the results to memory or a register.
Out-of-order execution - correct answer a situation in pipelined execution when an
instruction blocked from executing does not cause the following instructions to wait
In-order commit - correct answer a commit in which the results of pipelined execution
are written to the programmer visible state in the same order that instructions are
fetched
