Compute science—A Level—Comp 1 Topic 2—Processor
Internal structure of CPU
The Central processing unit is the brain of a
1. 2. computer and consists of registers, ALU and
control unit and responsible for the FDE cycle.
PC 6. MAR
Registers—Tiny areas of extremely fast
memory located in CPU, do specific tasks.
9. • Program counter
ACC -Holds the address of the next instruction to be
to be executed.
• Memory address register
8. -Stores the address of the memory location cur-
rently being used.
MDR • Memory data register
ALU 4. -stores data being transferred to and from main
memory.
• Current instruction register
-Located in CU, stores the address of current
Instruction being executed or decoded.
• Accumulator
5. -Special register in ALU, any data to be processed
Is stored here temporarily.
7. Other components in CPU
CU • Arithmetic logic unit
3. -data is processed and manipulated here (logic
comparisons and arithmetic operations).
The FDE cycle—Process of retrieving an instruction from store, decoding and executing it • Control unit
Fetch stage -Fetches instructions, decodes them and synchro
nises them before executing them by sending
• PC is checked as it holds the address of the next instruction to be executed. signals to other components of the computer.
• Address is coped into the MAR then sent along the address bus to main memory. Opcode=what to do
• CU sends a read signal through control bus to main memory. Operand=what to do it to
• The data stored in the certain address is sent to the MDR through the data bus.
• As we’re in the process of an instruction, it is sent to the CIR where it will be decoded. Buses—A physical pathway shared by signals
• Before the decode stage, the PC must be incremented by one to start the next fetch. to and from several different components.
Decode stage • Address bus (Unidirectional)
• The instruction contains two parts: the opcode and the operand code. Etc (01011000), 0101 is load and 1000 -Carries the identification about where the data
is the address it will load. Is being sent.
Execute stage • Data bus (Bidirectional)
• Address X is now sent to the MAR where it will be sent to main memory through the address bus. -Carries the actual information to or from the MDR
• A read signal is sent to main memory through control bus to allow us to read address x. • Control bus (Bidirectional)
• Data stored in address x is sent to the MDR through data bus. -Carries commands and control signals to and from
• The data in the MDR is copied into the ACC which is one of the general-purpose registers, the instruction every other component in a computer.
complete.
Von Neumann and Harvard Architecture + Contemporary architecture How the performance of the CPU can be affected
Von Neumann architecture A modern CPU can be affected by many factors, the 3 main are:
This is a traditional computer architecture
that forms the basis of most digital comput-
er systems.
• Shared memory space for instructions No. of cores Clock speed Cache size
and data.
Clock speed—Measured in Hz
• One instruction at a time. • Clock speed is the number of FDE cycles per second. (3.2Ghz is
• A single CU follows a linear FDE cycle. the average clock speed in modern CPUs, 3.2 billion cycles/s)
• Requires wide data bus to have extremely high clock speeds.
No. of cores
Harvard architecture
• Very simply, a duplicate copy of a CPU which has its own ALU etc.
• However, the more cores the longer it will take to synchronise all cores.
Cache size
• Small component located on the CPU which stores frequently used
instructions and data temporarily (Faster than main memory).
• We only need a small cache to see a significant increase in the performance.
How can pipelining further improve performance of CPU?
Pipelining is a method that the CPU follows, it’s a process where it can
run each step of the FDE cycle simultaneously which improves efficiency
A computer architecture with physically separate signal pathways of the CPU providing that there is a long sequence of instructions and no
and storages for instruction and data. conditions that flush the pipe (removing the previous instructions).
• Instructions and data stored separately in different memory units
with its own bus.
• Reading and writing data can be done at the same time as fetch-
ing an instruction.
Contemporary architectures—other modern architectures of building a CPU.
• An example is SIMD (Single instruction multiple data) which does parallel
processing where a single instruction is carried out on multiple data at a time.
Internal structure of CPU
The Central processing unit is the brain of a
1. 2. computer and consists of registers, ALU and
control unit and responsible for the FDE cycle.
PC 6. MAR
Registers—Tiny areas of extremely fast
memory located in CPU, do specific tasks.
9. • Program counter
ACC -Holds the address of the next instruction to be
to be executed.
• Memory address register
8. -Stores the address of the memory location cur-
rently being used.
MDR • Memory data register
ALU 4. -stores data being transferred to and from main
memory.
• Current instruction register
-Located in CU, stores the address of current
Instruction being executed or decoded.
• Accumulator
5. -Special register in ALU, any data to be processed
Is stored here temporarily.
7. Other components in CPU
CU • Arithmetic logic unit
3. -data is processed and manipulated here (logic
comparisons and arithmetic operations).
The FDE cycle—Process of retrieving an instruction from store, decoding and executing it • Control unit
Fetch stage -Fetches instructions, decodes them and synchro
nises them before executing them by sending
• PC is checked as it holds the address of the next instruction to be executed. signals to other components of the computer.
• Address is coped into the MAR then sent along the address bus to main memory. Opcode=what to do
• CU sends a read signal through control bus to main memory. Operand=what to do it to
• The data stored in the certain address is sent to the MDR through the data bus.
• As we’re in the process of an instruction, it is sent to the CIR where it will be decoded. Buses—A physical pathway shared by signals
• Before the decode stage, the PC must be incremented by one to start the next fetch. to and from several different components.
Decode stage • Address bus (Unidirectional)
• The instruction contains two parts: the opcode and the operand code. Etc (01011000), 0101 is load and 1000 -Carries the identification about where the data
is the address it will load. Is being sent.
Execute stage • Data bus (Bidirectional)
• Address X is now sent to the MAR where it will be sent to main memory through the address bus. -Carries the actual information to or from the MDR
• A read signal is sent to main memory through control bus to allow us to read address x. • Control bus (Bidirectional)
• Data stored in address x is sent to the MDR through data bus. -Carries commands and control signals to and from
• The data in the MDR is copied into the ACC which is one of the general-purpose registers, the instruction every other component in a computer.
complete.
Von Neumann and Harvard Architecture + Contemporary architecture How the performance of the CPU can be affected
Von Neumann architecture A modern CPU can be affected by many factors, the 3 main are:
This is a traditional computer architecture
that forms the basis of most digital comput-
er systems.
• Shared memory space for instructions No. of cores Clock speed Cache size
and data.
Clock speed—Measured in Hz
• One instruction at a time. • Clock speed is the number of FDE cycles per second. (3.2Ghz is
• A single CU follows a linear FDE cycle. the average clock speed in modern CPUs, 3.2 billion cycles/s)
• Requires wide data bus to have extremely high clock speeds.
No. of cores
Harvard architecture
• Very simply, a duplicate copy of a CPU which has its own ALU etc.
• However, the more cores the longer it will take to synchronise all cores.
Cache size
• Small component located on the CPU which stores frequently used
instructions and data temporarily (Faster than main memory).
• We only need a small cache to see a significant increase in the performance.
How can pipelining further improve performance of CPU?
Pipelining is a method that the CPU follows, it’s a process where it can
run each step of the FDE cycle simultaneously which improves efficiency
A computer architecture with physically separate signal pathways of the CPU providing that there is a long sequence of instructions and no
and storages for instruction and data. conditions that flush the pipe (removing the previous instructions).
• Instructions and data stored separately in different memory units
with its own bus.
• Reading and writing data can be done at the same time as fetch-
ing an instruction.
Contemporary architectures—other modern architectures of building a CPU.
• An example is SIMD (Single instruction multiple data) which does parallel
processing where a single instruction is carried out on multiple data at a time.
