STUDY NOTES & REFERENCE GUIDE
SoC Test Management
A Hierarchical Infrastructure
···
for SoC Test Management ··
Alfredo Benso, Stefano Di Carlo, and Paolo Prinetto Yervant Zorian
Politecnico di Torino Virage Logic
tectures that can fully support core reuse,
HD2BIST—a complete hierarchical framework for BIST scheduling, data- hierarchical design, and integration of
patterns delivery, and diagnosis of complex systems—maximizes and multiple test strategies. Direct accessibil-
simplifies the reuse of built-in test architectures. HD2BIST optimizes flexibility ity to interconnections and core bound-
for chip designers planning an overall SoC test strategy by defining a test aries is impossible in SoC test, but test
access method that provides direct virtual access to each core of the system. patterns still must travel from their source
to the core, and then to a sink. An access
architecture, or test access mechanism
THE CONSIDERABLE GROWTH of digital applica- (TAM), can solve this problem. The TAM must activate
tions such as communication systems has led to strong the test functions, possibly deliver test patterns, and
competition in the semiconductor industry. Part of the gather the test results for every core in the SoC hierar-
global economy’s success for at least the next decade chy. In general, a TAM must guarantee the following:
arguably hinges not only on how fast designers can devel-
op and manufacture new chips but also on how fast they ■ Core accessibility. TAMs should permit the control
can functionally test, diagnose, and verify them. Different core testing through a limited set of SoC boundary
test methods are possible, but the goal is always to help signals.
the industry grow and not slow it down. Complexity, per- ■ Reusability. Easy reconfigurability is necessary to
formance, and density, not to mention cost, will all manage the system cores’ different test architectures.
increase. Keeping up with these trends requires funda- ■ Minimal overhead. TAMs must have small area, rout-
mental changes in IC realization methods that directly ing, and performance overheads.
affect test methods, tools, and equipment. ■ Flexible test scheduling. TAMs should support core
Silicon area is now so cheap that a single SoC can test scheduling that minimizes power consumption
hold all the components and functions that historically during test execution.
required a hardware board. In addition, each compo-
nent or function is now available as a predesigned, The proposed IEEE Standard for Embedded Core
complex functional block. Often, this block comes as Test, P1500, will provide a plug-and-play methodology
an embedded IP core with an internal structure hidden to integrate core testability into a SoC. IEEE P1500 con-
from the core integrator. Moreover, each core can serve centrates on a standardized, configurable, and scalable
diverse scenarios and embed different test architectures core interface or wrapper that allows easy access to the
(such as full or partial scan, and BIST), so are reusable core’s internal-test methods. The TAM, which must man-
in different designs. Designers can also integrate cores age the execution of the test for the overall chip, is out
from different vendors. When a certain combination of of the current scope of IEEE P1500; therefore, the test
cores becomes common, a system integrator or core engineer must still design it.
provider can create a new core from that combination. Here, we present an innovative TAM, called hierar-
Hence, today’s SoCs could become tomorrow’s IP cores chical-distributed-data BIST (HD2BIST), that addresses
in more complex SoCs. several critical issues in SoC testing, including core
This new design philosophy, based on the hierar- accessibility and test reuse. This architecture allows
chical reuse of IP cores, requires system-level test archi- smooth integration and management of cores with dif-
32 0740-7475/03/$17.00 © 2003 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers
COURSESITY - Stuvia | Page 1 of 8
, STUDY NOTES & REFERENCE GUIDE
ferent test strategies and built-in test access ports approach. Implementing the TCB as a bidirectional link
(TAPs). The approach is fully compatible with the hier- guarantees its dependability: The same information
archical design methodology of SoCs, allowing access transmitted through a forward link returns via a back-
to any core in the system regardless of its hierarchical ward link to verify correctness. If a transmission error
depth. To reduce power consumption, HD2BIST sup- occurs, a diagnosis procedure can locate the fault.
ports test scheduling of cores using sophisticated con-
trol-flow mechanisms. Area overhead is very low Test block
because the HD2BIST architecture is fully customizable TBus is an efficient TAM only if a bus manager and
and adaptable to the test requirements of the cores inte- an appropriate bus interface with the cores under test
grated in the system. Thus, test engineers can trade off are properly defined and implemented. In HD2BIST, two
routing, area, and test length. In an IEEE-P1500-compli- special blocks—the test block (TB) and the test proces-
ant design, a significant part of the HD2BIST structures sor (TP)—perform these tasks. A unique address
would merge with the IEEE P1500 wrapper to optimize defined at design time identifies each core connected
performance and minimize area overhead. to TBus. Broadcast and group addresses add flexibility
and reduce the number of primitives necessary to exe-
TAM architecture
·
cute each test program.
For the sake of clarity, we introduce HD2BIST as a flat Engineers can easily customize the TB, shown in
architecture, but it actually has a hierarchical structure, Figure 1, to support the specific test solution imple-
fully adaptable to the hierarchical architecture of com- mented in the core. We optimized the TB’s internal
plex SoCs. (The “State-of-the-Art TAMs” sidebar dis- structure for
cusses other proposed TAM architectures.)
■ full- and partial-scan cores, using the TDB to apply
Test bus test vectors and gather test results;
The main actor in HD2BIST is the test bus (TBus) ■ BIST-enabled cores, using the TCB to send BIST com-
communication link, which provides an effective solu- mands and read BIST results; and
tion for core accessibility and TAM reuse. The data ■ BIST-ready cores, using the TDB to exchange test
exchanged over TBus falls into two categories: vectors between the core under test and its BIST
controller.
■ Control data configures and controls all the HD2BIST
test structures. Test process
■ Test data carries the test vectors for testing the sys- Through TBus, the TP controls all HD2BIST structures
tem-embedded cores. Test vectors can come from inserted in the chip and schedules the test execution for
the on-chip BIST controllers or from outside the chip. each core in the chip. To make this task as flexible as
possible, we interface the TP to TBus through a lower-
To reflect this logical classification, we split TBus into level interface, as Figure 2 shows. We can implement
the test control bus (TCB) and the test data bus (TDB). the interface as either a finite-state machine or a micro-
By implementing these as a ring bus, we can guarantee programmed machine. It executes a sequence of test
a simple, technology-independent approach and offer primitives, implementing a set of test programs defined
high flexibility and dependability. by the core integrator. Each test primitive corresponds
Because the information exchanged on the two buses to one or more tokens exchanged over the TCB; so test
differs, each uses different communication protocols. primitives are either TP generated or come from outside
Control data on the TCB is typically easily encodable as a the SoC through a Joint Test Access Group interface.
predefined set of commands, called test primitives. The JTAG interface lets a standardized protocol access
Therefore, we chose a token-based protocol for the TCB. the TP and the HD2BIST structure to control execution
Data on the TDB, on the other hand, often involves many of the test programs from an external tester.
test patterns and test responses. Hence, we chose a scan- To accommodate the SoC hierarchical design
chain-based protocol to transmit TDB data. approach, HD2BIST lets you connect different TBus com-
TBus structure implemented by HD2BIST provides munication links together via the TP. In this case, a TB-like
high reliability. Thanks to the scan chain protocol, we interface called the upper-level interface connects the TP
can easily test the TDB using a standard scan-test of one TBus to a second TBus, as Figure 3 shows. Each TP
July–August 2003
33
COURSESITY - Stuvia | Page 2 of 8
SoC Test Management
A Hierarchical Infrastructure
···
for SoC Test Management ··
Alfredo Benso, Stefano Di Carlo, and Paolo Prinetto Yervant Zorian
Politecnico di Torino Virage Logic
tectures that can fully support core reuse,
HD2BIST—a complete hierarchical framework for BIST scheduling, data- hierarchical design, and integration of
patterns delivery, and diagnosis of complex systems—maximizes and multiple test strategies. Direct accessibil-
simplifies the reuse of built-in test architectures. HD2BIST optimizes flexibility ity to interconnections and core bound-
for chip designers planning an overall SoC test strategy by defining a test aries is impossible in SoC test, but test
access method that provides direct virtual access to each core of the system. patterns still must travel from their source
to the core, and then to a sink. An access
architecture, or test access mechanism
THE CONSIDERABLE GROWTH of digital applica- (TAM), can solve this problem. The TAM must activate
tions such as communication systems has led to strong the test functions, possibly deliver test patterns, and
competition in the semiconductor industry. Part of the gather the test results for every core in the SoC hierar-
global economy’s success for at least the next decade chy. In general, a TAM must guarantee the following:
arguably hinges not only on how fast designers can devel-
op and manufacture new chips but also on how fast they ■ Core accessibility. TAMs should permit the control
can functionally test, diagnose, and verify them. Different core testing through a limited set of SoC boundary
test methods are possible, but the goal is always to help signals.
the industry grow and not slow it down. Complexity, per- ■ Reusability. Easy reconfigurability is necessary to
formance, and density, not to mention cost, will all manage the system cores’ different test architectures.
increase. Keeping up with these trends requires funda- ■ Minimal overhead. TAMs must have small area, rout-
mental changes in IC realization methods that directly ing, and performance overheads.
affect test methods, tools, and equipment. ■ Flexible test scheduling. TAMs should support core
Silicon area is now so cheap that a single SoC can test scheduling that minimizes power consumption
hold all the components and functions that historically during test execution.
required a hardware board. In addition, each compo-
nent or function is now available as a predesigned, The proposed IEEE Standard for Embedded Core
complex functional block. Often, this block comes as Test, P1500, will provide a plug-and-play methodology
an embedded IP core with an internal structure hidden to integrate core testability into a SoC. IEEE P1500 con-
from the core integrator. Moreover, each core can serve centrates on a standardized, configurable, and scalable
diverse scenarios and embed different test architectures core interface or wrapper that allows easy access to the
(such as full or partial scan, and BIST), so are reusable core’s internal-test methods. The TAM, which must man-
in different designs. Designers can also integrate cores age the execution of the test for the overall chip, is out
from different vendors. When a certain combination of of the current scope of IEEE P1500; therefore, the test
cores becomes common, a system integrator or core engineer must still design it.
provider can create a new core from that combination. Here, we present an innovative TAM, called hierar-
Hence, today’s SoCs could become tomorrow’s IP cores chical-distributed-data BIST (HD2BIST), that addresses
in more complex SoCs. several critical issues in SoC testing, including core
This new design philosophy, based on the hierar- accessibility and test reuse. This architecture allows
chical reuse of IP cores, requires system-level test archi- smooth integration and management of cores with dif-
32 0740-7475/03/$17.00 © 2003 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers
COURSESITY - Stuvia | Page 1 of 8
, STUDY NOTES & REFERENCE GUIDE
ferent test strategies and built-in test access ports approach. Implementing the TCB as a bidirectional link
(TAPs). The approach is fully compatible with the hier- guarantees its dependability: The same information
archical design methodology of SoCs, allowing access transmitted through a forward link returns via a back-
to any core in the system regardless of its hierarchical ward link to verify correctness. If a transmission error
depth. To reduce power consumption, HD2BIST sup- occurs, a diagnosis procedure can locate the fault.
ports test scheduling of cores using sophisticated con-
trol-flow mechanisms. Area overhead is very low Test block
because the HD2BIST architecture is fully customizable TBus is an efficient TAM only if a bus manager and
and adaptable to the test requirements of the cores inte- an appropriate bus interface with the cores under test
grated in the system. Thus, test engineers can trade off are properly defined and implemented. In HD2BIST, two
routing, area, and test length. In an IEEE-P1500-compli- special blocks—the test block (TB) and the test proces-
ant design, a significant part of the HD2BIST structures sor (TP)—perform these tasks. A unique address
would merge with the IEEE P1500 wrapper to optimize defined at design time identifies each core connected
performance and minimize area overhead. to TBus. Broadcast and group addresses add flexibility
and reduce the number of primitives necessary to exe-
TAM architecture
·
cute each test program.
For the sake of clarity, we introduce HD2BIST as a flat Engineers can easily customize the TB, shown in
architecture, but it actually has a hierarchical structure, Figure 1, to support the specific test solution imple-
fully adaptable to the hierarchical architecture of com- mented in the core. We optimized the TB’s internal
plex SoCs. (The “State-of-the-Art TAMs” sidebar dis- structure for
cusses other proposed TAM architectures.)
■ full- and partial-scan cores, using the TDB to apply
Test bus test vectors and gather test results;
The main actor in HD2BIST is the test bus (TBus) ■ BIST-enabled cores, using the TCB to send BIST com-
communication link, which provides an effective solu- mands and read BIST results; and
tion for core accessibility and TAM reuse. The data ■ BIST-ready cores, using the TDB to exchange test
exchanged over TBus falls into two categories: vectors between the core under test and its BIST
controller.
■ Control data configures and controls all the HD2BIST
test structures. Test process
■ Test data carries the test vectors for testing the sys- Through TBus, the TP controls all HD2BIST structures
tem-embedded cores. Test vectors can come from inserted in the chip and schedules the test execution for
the on-chip BIST controllers or from outside the chip. each core in the chip. To make this task as flexible as
possible, we interface the TP to TBus through a lower-
To reflect this logical classification, we split TBus into level interface, as Figure 2 shows. We can implement
the test control bus (TCB) and the test data bus (TDB). the interface as either a finite-state machine or a micro-
By implementing these as a ring bus, we can guarantee programmed machine. It executes a sequence of test
a simple, technology-independent approach and offer primitives, implementing a set of test programs defined
high flexibility and dependability. by the core integrator. Each test primitive corresponds
Because the information exchanged on the two buses to one or more tokens exchanged over the TCB; so test
differs, each uses different communication protocols. primitives are either TP generated or come from outside
Control data on the TCB is typically easily encodable as a the SoC through a Joint Test Access Group interface.
predefined set of commands, called test primitives. The JTAG interface lets a standardized protocol access
Therefore, we chose a token-based protocol for the TCB. the TP and the HD2BIST structure to control execution
Data on the TDB, on the other hand, often involves many of the test programs from an external tester.
test patterns and test responses. Hence, we chose a scan- To accommodate the SoC hierarchical design
chain-based protocol to transmit TDB data. approach, HD2BIST lets you connect different TBus com-
TBus structure implemented by HD2BIST provides munication links together via the TP. In this case, a TB-like
high reliability. Thanks to the scan chain protocol, we interface called the upper-level interface connects the TP
can easily test the TDB using a standard scan-test of one TBus to a second TBus, as Figure 3 shows. Each TP
July–August 2003
33
COURSESITY - Stuvia | Page 2 of 8
