STUVIA EXAM LIBRARY
EXAMINATION DOCUMENT 2026/2027 • WGU D386
■ COMPUTER ARCHITECTURE | CPU • ISA • PERFORMANCE
D386 Exam 1 - Architecture Fundamentals
D386 Computer Architecture and Operating Systems Exam 1 2026/2027 - Computer Architecture Fundamentals Performance ISA Focus - 210
Q&A; - A+ Graded - Latest Update This Year - Just Released - Verified Solutions - Pass Guaranteed
★ A+ VERIFIED ★ WGU D386 • 210 Q&A; • 2026/2027
Focus: Computer architecture history, Von Neumann, performance metrics CPI, MIPS, Amdahl's law, instruction set
architectures RISC CISC, addressing modes
, Table of Contents - D386 Exam 1 - 100% Unique Architecture Fundamentals
Structure
1. Part I: Historical Evolution of Stored-Program Concepts and First Generation Milestones
........................................................... 11
2. Part II: Von Neumann Model Deep Dive Bottleneck Analysis and Register Transfer Logic
........................................................... 22
3. Part III: Quantitative Performance Engineering – Iron Law, CPI Stacks, and Cycle Accounting
........................................................... 33
4. Part IV: MIPS Throughput, SPEC Benchmarking, and ISA-Dependent Metric Pitfalls
........................................................... 44
5. Part V: Amdahl's Law Applied – Scalability Limits, Accelerator ROI, and Parallel Fractioning
........................................................... 55
6. Part VI: RISC Design Tenets versus CISC Complexity Tradeoffs in Modern Hybrid Cores
........................................................... 66
7. Part VII: Addressing Mode Taxonomy, Effective Address Generation, and Position-Independent Code
........................................................... 77
8. Part VIII: Full Practice Examination – 210 Scenario-Based Calculation and Design Decisions
........................................................... 88
9. Part IX: Answer Key Distribution Map with Verified Rationales Highlighted
........................................................... 99
10. Part X: WGU D386 Study Framework Mapping Objectives to Performance Domains 2026/2027
........................................................... 110
STUVIA EXAM LIBRARY - D386 Exam 1 - Architecture Fundamentals - A+ VERIFIED 2026/2027 Page 2
, D386 Exam 1 – Architecture Fundamentals – 210 Questions & Answers – WGU
Style Scenario Based
Instructions: Select best answer (A-D). Each question includes yellow-highlighted rationale (80-120 words). Answers
randomized ~25% each. WGU performance calculation focus.
Q1. WGU benchmark analysis: System X clock 3054 MHz, executes 7,601,096 instructions with
CPI 2.32. A competitor claims higher MIPS but uses different instruction count for same
workload. Calculate MIPS for System X and evaluate why MIPS alone can be misleading across
ISAs. Which statement is correct?
A. 394.9 MIPS because MIPS always equals clock rate regardless of CPI
B. 7.6 MIPS calculated solely from IC ignoring clock rate
C. 2369.5 MIPS and is universally comparable across all architectures without normalization
D. 1316.4 MIPS with caveat that MIPS varies with instruction count and does not account for work done per
instruction across RISC/CISC
Correct Answer: D
Rationale: MIPS = Clock Rate / (CPI * 10^6) for this simplification or IC/(Time*10^6). Here 3054 MHz / 2.32 = 1316.4
MIPS. The key learning for D386 is that MIPS is ISA-dependent: CISC may do more work per instruction than RISC, so
higher MIPS does not guarantee faster execution for same high-level program. Benchmarks like SPEC CPU address
this by using execution time on reference workloads. Incorrect options misuse formula or overgeneralize comparability,
a common trap in WGU performance questions.
Q2. WGU benchmark analysis: System X clock 2653 MHz, executes 6,912,419 instructions with
CPI 2.35. A competitor claims higher MIPS but uses different instruction count for same
workload. Calculate MIPS for System X and evaluate why MIPS alone can be misleading across
ISAs. Which statement is correct?
A. 2032.0 MIPS and is universally comparable across all architectures without normalization
B. 6.9 MIPS calculated solely from IC ignoring clock rate
C. 1128.9 MIPS with caveat that MIPS varies with instruction count and does not account for work done per
instruction across RISC/CISC
D. 338.7 MIPS because MIPS always equals clock rate regardless of CPI
Correct Answer: C
Rationale: MIPS = Clock Rate / (CPI * 10^6) for this simplification or IC/(Time*10^6). Here 2653 MHz / 2.35 = 1128.9
MIPS. The key learning for D386 is that MIPS is ISA-dependent: CISC may do more work per instruction than RISC, so
higher MIPS does not guarantee faster execution for same high-level program. Benchmarks like SPEC CPU address
this by using execution time on reference workloads. Incorrect options misuse formula or overgeneralize comparability,
a common trap in WGU performance questions.
STUVIA EXAM LIBRARY - D386 Exam 1 - Architecture Fundamentals - A+ VERIFIED 2026/2027 Page 3
, Q3. Scenario: D386 assembly debugging: Instruction LDA #500 uses #Base-plus-offset style
notation. Memory at 0x1000 contains 0x2000, register R1=0x1000, R2=0x2000. For question 204,
given Base-plus-offset addressing mode, what is effective address calculation? Identify correct
definition for Base-plus-offset addressing in WGU architecture simulator:
A. Immediate: operand value is in instruction itself, e.g., ADD #5 adds constant 5 without memory access
B. Immediate: operand is memory address pointed by PC plus offset 5
C. Immediate: operand requires two memory dereferences via pointer chain
D. Immediate: operand is in cache only and never in instruction word
Correct Answer: A
Rationale: The rationale for Base-plus-offset addressing mode centers on immediate addressing embeds constant
operand within instruction word, eliminating memory fetch for operand, useful for constants and fast execution. In a
WGU scenario, you must differentiate true performance gain from architectural marketing claims. Distractors confuse
with direct or indirect definitions Each wrong answer either violates Von Neumann stored-program concept,
miscalculates Amdahl's law, or incorrectly classifies RISC/CISC traits. The exam emphasizes quantitative reasoning
and accurate addressing mode identification. Apply systematic elimination and verify units in calculations.
Q4. Case 28: WGU archival research shows early architecture milestone. Question 28 focuses
on microprocessor birth. Specifically, how did family of compatible machines shape
cost/performance tradeoff? What is the most accurate historical interpretation?
A. Introduction of stored-program concept allowing instructions and data to share memory, as described in First
Draft of Report on EDVAC
B. Development of GPU acceleration for graphics rendering in 1940s
C. Use of quantum entanglement for memory addressing in early computers
D. Implementation of Internet protocol stack in vacuum tube machines
Correct Answer: A
Rationale: For computer architecture history, the principle states that the EDVAC report formalized stored programs,
enabling sequential fetch-decode-execute, which is foundational to Von Neumann machines and still used today. This
is a core competency in D386 Exam 1 focusing on fundamentals. Other options are anachronistic or irrelevant to the
1940s era The distractors represent common misconceptions such as conflating throughput with latency or misapplying
von Neumann bottleneck assumptions. Mastery requires linking historical context to modern metrics like CPI and MIPS.
Review lecture notes on instruction execution and benchmark interpretation to reinforce this concept for WGU
assessments.
STUVIA EXAM LIBRARY - D386 Exam 1 - Architecture Fundamentals - A+ VERIFIED 2026/2027 Page 4
EXAMINATION DOCUMENT 2026/2027 • WGU D386
■ COMPUTER ARCHITECTURE | CPU • ISA • PERFORMANCE
D386 Exam 1 - Architecture Fundamentals
D386 Computer Architecture and Operating Systems Exam 1 2026/2027 - Computer Architecture Fundamentals Performance ISA Focus - 210
Q&A; - A+ Graded - Latest Update This Year - Just Released - Verified Solutions - Pass Guaranteed
★ A+ VERIFIED ★ WGU D386 • 210 Q&A; • 2026/2027
Focus: Computer architecture history, Von Neumann, performance metrics CPI, MIPS, Amdahl's law, instruction set
architectures RISC CISC, addressing modes
, Table of Contents - D386 Exam 1 - 100% Unique Architecture Fundamentals
Structure
1. Part I: Historical Evolution of Stored-Program Concepts and First Generation Milestones
........................................................... 11
2. Part II: Von Neumann Model Deep Dive Bottleneck Analysis and Register Transfer Logic
........................................................... 22
3. Part III: Quantitative Performance Engineering – Iron Law, CPI Stacks, and Cycle Accounting
........................................................... 33
4. Part IV: MIPS Throughput, SPEC Benchmarking, and ISA-Dependent Metric Pitfalls
........................................................... 44
5. Part V: Amdahl's Law Applied – Scalability Limits, Accelerator ROI, and Parallel Fractioning
........................................................... 55
6. Part VI: RISC Design Tenets versus CISC Complexity Tradeoffs in Modern Hybrid Cores
........................................................... 66
7. Part VII: Addressing Mode Taxonomy, Effective Address Generation, and Position-Independent Code
........................................................... 77
8. Part VIII: Full Practice Examination – 210 Scenario-Based Calculation and Design Decisions
........................................................... 88
9. Part IX: Answer Key Distribution Map with Verified Rationales Highlighted
........................................................... 99
10. Part X: WGU D386 Study Framework Mapping Objectives to Performance Domains 2026/2027
........................................................... 110
STUVIA EXAM LIBRARY - D386 Exam 1 - Architecture Fundamentals - A+ VERIFIED 2026/2027 Page 2
, D386 Exam 1 – Architecture Fundamentals – 210 Questions & Answers – WGU
Style Scenario Based
Instructions: Select best answer (A-D). Each question includes yellow-highlighted rationale (80-120 words). Answers
randomized ~25% each. WGU performance calculation focus.
Q1. WGU benchmark analysis: System X clock 3054 MHz, executes 7,601,096 instructions with
CPI 2.32. A competitor claims higher MIPS but uses different instruction count for same
workload. Calculate MIPS for System X and evaluate why MIPS alone can be misleading across
ISAs. Which statement is correct?
A. 394.9 MIPS because MIPS always equals clock rate regardless of CPI
B. 7.6 MIPS calculated solely from IC ignoring clock rate
C. 2369.5 MIPS and is universally comparable across all architectures without normalization
D. 1316.4 MIPS with caveat that MIPS varies with instruction count and does not account for work done per
instruction across RISC/CISC
Correct Answer: D
Rationale: MIPS = Clock Rate / (CPI * 10^6) for this simplification or IC/(Time*10^6). Here 3054 MHz / 2.32 = 1316.4
MIPS. The key learning for D386 is that MIPS is ISA-dependent: CISC may do more work per instruction than RISC, so
higher MIPS does not guarantee faster execution for same high-level program. Benchmarks like SPEC CPU address
this by using execution time on reference workloads. Incorrect options misuse formula or overgeneralize comparability,
a common trap in WGU performance questions.
Q2. WGU benchmark analysis: System X clock 2653 MHz, executes 6,912,419 instructions with
CPI 2.35. A competitor claims higher MIPS but uses different instruction count for same
workload. Calculate MIPS for System X and evaluate why MIPS alone can be misleading across
ISAs. Which statement is correct?
A. 2032.0 MIPS and is universally comparable across all architectures without normalization
B. 6.9 MIPS calculated solely from IC ignoring clock rate
C. 1128.9 MIPS with caveat that MIPS varies with instruction count and does not account for work done per
instruction across RISC/CISC
D. 338.7 MIPS because MIPS always equals clock rate regardless of CPI
Correct Answer: C
Rationale: MIPS = Clock Rate / (CPI * 10^6) for this simplification or IC/(Time*10^6). Here 2653 MHz / 2.35 = 1128.9
MIPS. The key learning for D386 is that MIPS is ISA-dependent: CISC may do more work per instruction than RISC, so
higher MIPS does not guarantee faster execution for same high-level program. Benchmarks like SPEC CPU address
this by using execution time on reference workloads. Incorrect options misuse formula or overgeneralize comparability,
a common trap in WGU performance questions.
STUVIA EXAM LIBRARY - D386 Exam 1 - Architecture Fundamentals - A+ VERIFIED 2026/2027 Page 3
, Q3. Scenario: D386 assembly debugging: Instruction LDA #500 uses #Base-plus-offset style
notation. Memory at 0x1000 contains 0x2000, register R1=0x1000, R2=0x2000. For question 204,
given Base-plus-offset addressing mode, what is effective address calculation? Identify correct
definition for Base-plus-offset addressing in WGU architecture simulator:
A. Immediate: operand value is in instruction itself, e.g., ADD #5 adds constant 5 without memory access
B. Immediate: operand is memory address pointed by PC plus offset 5
C. Immediate: operand requires two memory dereferences via pointer chain
D. Immediate: operand is in cache only and never in instruction word
Correct Answer: A
Rationale: The rationale for Base-plus-offset addressing mode centers on immediate addressing embeds constant
operand within instruction word, eliminating memory fetch for operand, useful for constants and fast execution. In a
WGU scenario, you must differentiate true performance gain from architectural marketing claims. Distractors confuse
with direct or indirect definitions Each wrong answer either violates Von Neumann stored-program concept,
miscalculates Amdahl's law, or incorrectly classifies RISC/CISC traits. The exam emphasizes quantitative reasoning
and accurate addressing mode identification. Apply systematic elimination and verify units in calculations.
Q4. Case 28: WGU archival research shows early architecture milestone. Question 28 focuses
on microprocessor birth. Specifically, how did family of compatible machines shape
cost/performance tradeoff? What is the most accurate historical interpretation?
A. Introduction of stored-program concept allowing instructions and data to share memory, as described in First
Draft of Report on EDVAC
B. Development of GPU acceleration for graphics rendering in 1940s
C. Use of quantum entanglement for memory addressing in early computers
D. Implementation of Internet protocol stack in vacuum tube machines
Correct Answer: A
Rationale: For computer architecture history, the principle states that the EDVAC report formalized stored programs,
enabling sequential fetch-decode-execute, which is foundational to Von Neumann machines and still used today. This
is a core competency in D386 Exam 1 focusing on fundamentals. Other options are anachronistic or irrelevant to the
1940s era The distractors represent common misconceptions such as conflating throughput with latency or misapplying
von Neumann bottleneck assumptions. Mastery requires linking historical context to modern metrics like CPI and MIPS.
Review lecture notes on instruction execution and benchmark interpretation to reinforce this concept for WGU
assessments.
STUVIA EXAM LIBRARY - D386 Exam 1 - Architecture Fundamentals - A+ VERIFIED 2026/2027 Page 4
