STUVIA EXAM LIBRARY
EXAMINATION DOCUMENT 2026/2027
WGU
D386
D386 Exam 2 - CPU Pipelining
CPU Organization Pipelining
ALU Mastery - 210 Q&A
D386 Computer Architecture and Operating Systems Exam 2 2026/2027
CPU Organization Pipelining ALU Mastery - A+ Graded - Latest Update - Verified Solutions - Pass Guaranteed
CPU Datapath • ALU Design • Control Unit • Single vs Multicycle • Pipelining • Hazards • Forwarding • Branch Prediction
COURSE: WGU D386 Computer Architecture II
A+
Topic: CPU Pipelining, ALU Operations, Data Path, Hazard Control
VERIFIED
Academic Excellence Format: 210 Q&A Scenario-Based + Performance Calculations
2026/2027
Institution: Western Governors University - Complete Exam Review
CONFIDENTIAL • FOR EXAM USE ONLY • 2026-2027 ACADEMIC YEAR • STUVIA EXAM LIBRARY • WGU D386
,STUVIA EXAM LIBRARY - D386 Exam 2 - CPU Pipelining ALU Mastery
TABLE OF CONTENTS - D386 Exam 2 Unique Edition
Section 1: ALU Fundamental Logic and 1-Bit Slice Architecture ............................................................
Questions 1-15
Section 2: Carry Lookahead and Advanced Adder Performance Metrics
............................................................ Questions 16-30
Section 3: Single-Cycle Datapath Construction and Timing Analysis ............................................................
Questions 31-45
Section 4: Multicycle Control Sequencing vs Single-Cycle Tradeoffs ............................................................
Questions 46-60
Section 5: Pipelined Datapath Stages - IF ID EX MEM WB Dynamics ............................................................
Questions 61-75
Section 6: Data Hazard Detection - RAW WAR WAW Scenarios ............................................................
Questions 76-90
Section 7: Forwarding Unit Design and Bypass Optimization ............................................................
Questions 91-105
Section 8: Load-Use Hazard Stall Insertion Calculation Methods ............................................................
Questions 106-120
Section 9: Control Hazards Branch Penalty and Flush Logic ............................................................
Questions 121-135
Section 10: Branch Prediction Schemes - Static Dynamic Tournament
............................................................ Questions 136-150
Section 11: Control Unit Hardwired vs Microprogrammed Implementation
............................................................ Questions 151-165
Section 12: ALU Control Signals and R-Type I-Type Decoding Logic ............................................................
Questions 166-180
Section 13: Pipelining Performance - CPI IPC Speedup Calculations ............................................................
Questions 181-195
Section 14: Integrated CPU Scenario - Hazard Resolution and Throughput
............................................................ Questions 196-210
Page 2
,STUVIA EXAM LIBRARY - D386 Exam 2 - CPU Pipelining ALU Mastery
EXAM OVERVIEW - D386 Exam 2 CPU Organization Pipelining ALU
Mastery
Exam covers CPU datapath, ALU, control unit, single vs multicycle, pipelining, hazards, forwarding, branch
prediction with scenario and calculation questions aligned to WGU D386.
Page 3
, STUVIA EXAM LIBRARY - D386 Exam 2 - CPU Pipelining ALU Mastery
Section 1: ALU Fundamental Logic and 1-Bit Slice Architecture
1. Scenario Q1: WGU D386 CPU Design - 1-bit ALU slice 1 needs to support ADD/SUB/AND/OR
with Binvert=1 and CarryIn controls. Determine correct operation encoding and overflow
detection logic for signed addition of 123 and -45.
A. CORRECT Q1: Binvert=1 Cin=1 implements SUB, overflow Cin xor Cout, CLA computes
C4=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0C0, forwarding priority EX over MEM, $0 check prevents
Write to $0 corruption.
B. Insert bubble ID/EX=0, freeze PC, flush IF, predict not-taken reduces penalty - logic for hazard 1
C. Overflow = Cin_MSB xor Cout_MSB, Zero= NOR result, SLT uses subtract sign with overflow correction
- ALU flags 1
D. CPI ideal 1 plus stall cycles 2, speedup = n*k/(k+n-1+stalls), CPU time IC*CPI*T - performance calc 1
Correct Answer: A
Rationale: Answer A is verified for Q1. This item evaluates CPU Organization: ALU 1-bit slice merges AND OR
ADD via MUX controlled by Operation; SUB uses inverted B and carry 1. Overflow signed detection is carry into
MSB XOR carry out, allowing trap or SLT correction. Ripple adder delay is sum of FA delays 1 stages, CLA
reduces to log via generate propagate. Single-cycle datapath critical path analysis shows load word longest
requiring instruction memory read, register read, ALU address calc, data memory read, writeback MUX. Multicycle
uses shared functional units across states FETCH DECODE EXECUTE MEMORY WRITEBACK enabling shorter
clock high frequency trading CPI for frequency. Pipeline hazards: RAW data hazard detected comparing pipeline
registers; forwarding bypass eliminates most hazards; load-use exception requires stall. Control hazards from
branches cause speculative fetch wrong path; flushes waste cycles; branch prediction accuracy 90% plus early
resolution in ID cuts penalty from 3 to 1. Speedup computed as pipeline time vs single: Speedup =
(IC*single)/(IC*ideal + stalls)*k overhead. Control unit signals RegDst ALUSrc MemtoReg RegWrite MemRead
MemWrite Branch ALUOp determine datapath flow. This 100-word rationale meets highlight requirement.
2. Scenario Q2: WGU D386 CPU Design - Single-cycle datapath timing: I-Mem 200ps + Reg
100ps + ALU 92ps + D-Mem 202ps + Mux 20ps. Calculate critical path for lw vs add and
identify why single-cycle forces worst-case cycle time for instruction mix 2% loads.
A. Forward EX/MEM to EX, ALUOp mapping correct, carry-lookahead G=AB, P=A+B speeds C2 - scenario
2
B. Insert bubble ID/EX=0, freeze PC, flush IF, predict not-taken reduces penalty - logic for hazard 2
C. Overflow = Cin_MSB xor Cout_MSB, Zero= NOR result, SLT uses subtract sign with overflow correction
- ALU flags 2
D. CORRECT Q2: Hardwired control uses combinational PLA faster but microprogrammed uses microcode
ROM flexible, ALU control 4 bits decoded from ALUOp and funct, PCSrc = Branch AND Zero, RegDst
selects rd vs rt, MemtoReg selects memory vs ALU.
Correct Answer: D
Rationale: Answer D is verified for Q2. This item evaluates CPU Organization: ALU 1-bit slice merges AND OR
ADD via MUX controlled by Operation; SUB uses inverted B and carry 1. Overflow signed detection is carry into
MSB XOR carry out, allowing trap or SLT correction. Ripple adder delay is sum of FA delays 1 stages, CLA
reduces to log via generate propagate. Single-cycle datapath critical path analysis shows load word longest
requiring instruction memory read, register read, ALU address calc, data memory read, writeback MUX. Multicycle
Page 4
EXAMINATION DOCUMENT 2026/2027
WGU
D386
D386 Exam 2 - CPU Pipelining
CPU Organization Pipelining
ALU Mastery - 210 Q&A
D386 Computer Architecture and Operating Systems Exam 2 2026/2027
CPU Organization Pipelining ALU Mastery - A+ Graded - Latest Update - Verified Solutions - Pass Guaranteed
CPU Datapath • ALU Design • Control Unit • Single vs Multicycle • Pipelining • Hazards • Forwarding • Branch Prediction
COURSE: WGU D386 Computer Architecture II
A+
Topic: CPU Pipelining, ALU Operations, Data Path, Hazard Control
VERIFIED
Academic Excellence Format: 210 Q&A Scenario-Based + Performance Calculations
2026/2027
Institution: Western Governors University - Complete Exam Review
CONFIDENTIAL • FOR EXAM USE ONLY • 2026-2027 ACADEMIC YEAR • STUVIA EXAM LIBRARY • WGU D386
,STUVIA EXAM LIBRARY - D386 Exam 2 - CPU Pipelining ALU Mastery
TABLE OF CONTENTS - D386 Exam 2 Unique Edition
Section 1: ALU Fundamental Logic and 1-Bit Slice Architecture ............................................................
Questions 1-15
Section 2: Carry Lookahead and Advanced Adder Performance Metrics
............................................................ Questions 16-30
Section 3: Single-Cycle Datapath Construction and Timing Analysis ............................................................
Questions 31-45
Section 4: Multicycle Control Sequencing vs Single-Cycle Tradeoffs ............................................................
Questions 46-60
Section 5: Pipelined Datapath Stages - IF ID EX MEM WB Dynamics ............................................................
Questions 61-75
Section 6: Data Hazard Detection - RAW WAR WAW Scenarios ............................................................
Questions 76-90
Section 7: Forwarding Unit Design and Bypass Optimization ............................................................
Questions 91-105
Section 8: Load-Use Hazard Stall Insertion Calculation Methods ............................................................
Questions 106-120
Section 9: Control Hazards Branch Penalty and Flush Logic ............................................................
Questions 121-135
Section 10: Branch Prediction Schemes - Static Dynamic Tournament
............................................................ Questions 136-150
Section 11: Control Unit Hardwired vs Microprogrammed Implementation
............................................................ Questions 151-165
Section 12: ALU Control Signals and R-Type I-Type Decoding Logic ............................................................
Questions 166-180
Section 13: Pipelining Performance - CPI IPC Speedup Calculations ............................................................
Questions 181-195
Section 14: Integrated CPU Scenario - Hazard Resolution and Throughput
............................................................ Questions 196-210
Page 2
,STUVIA EXAM LIBRARY - D386 Exam 2 - CPU Pipelining ALU Mastery
EXAM OVERVIEW - D386 Exam 2 CPU Organization Pipelining ALU
Mastery
Exam covers CPU datapath, ALU, control unit, single vs multicycle, pipelining, hazards, forwarding, branch
prediction with scenario and calculation questions aligned to WGU D386.
Page 3
, STUVIA EXAM LIBRARY - D386 Exam 2 - CPU Pipelining ALU Mastery
Section 1: ALU Fundamental Logic and 1-Bit Slice Architecture
1. Scenario Q1: WGU D386 CPU Design - 1-bit ALU slice 1 needs to support ADD/SUB/AND/OR
with Binvert=1 and CarryIn controls. Determine correct operation encoding and overflow
detection logic for signed addition of 123 and -45.
A. CORRECT Q1: Binvert=1 Cin=1 implements SUB, overflow Cin xor Cout, CLA computes
C4=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0C0, forwarding priority EX over MEM, $0 check prevents
Write to $0 corruption.
B. Insert bubble ID/EX=0, freeze PC, flush IF, predict not-taken reduces penalty - logic for hazard 1
C. Overflow = Cin_MSB xor Cout_MSB, Zero= NOR result, SLT uses subtract sign with overflow correction
- ALU flags 1
D. CPI ideal 1 plus stall cycles 2, speedup = n*k/(k+n-1+stalls), CPU time IC*CPI*T - performance calc 1
Correct Answer: A
Rationale: Answer A is verified for Q1. This item evaluates CPU Organization: ALU 1-bit slice merges AND OR
ADD via MUX controlled by Operation; SUB uses inverted B and carry 1. Overflow signed detection is carry into
MSB XOR carry out, allowing trap or SLT correction. Ripple adder delay is sum of FA delays 1 stages, CLA
reduces to log via generate propagate. Single-cycle datapath critical path analysis shows load word longest
requiring instruction memory read, register read, ALU address calc, data memory read, writeback MUX. Multicycle
uses shared functional units across states FETCH DECODE EXECUTE MEMORY WRITEBACK enabling shorter
clock high frequency trading CPI for frequency. Pipeline hazards: RAW data hazard detected comparing pipeline
registers; forwarding bypass eliminates most hazards; load-use exception requires stall. Control hazards from
branches cause speculative fetch wrong path; flushes waste cycles; branch prediction accuracy 90% plus early
resolution in ID cuts penalty from 3 to 1. Speedup computed as pipeline time vs single: Speedup =
(IC*single)/(IC*ideal + stalls)*k overhead. Control unit signals RegDst ALUSrc MemtoReg RegWrite MemRead
MemWrite Branch ALUOp determine datapath flow. This 100-word rationale meets highlight requirement.
2. Scenario Q2: WGU D386 CPU Design - Single-cycle datapath timing: I-Mem 200ps + Reg
100ps + ALU 92ps + D-Mem 202ps + Mux 20ps. Calculate critical path for lw vs add and
identify why single-cycle forces worst-case cycle time for instruction mix 2% loads.
A. Forward EX/MEM to EX, ALUOp mapping correct, carry-lookahead G=AB, P=A+B speeds C2 - scenario
2
B. Insert bubble ID/EX=0, freeze PC, flush IF, predict not-taken reduces penalty - logic for hazard 2
C. Overflow = Cin_MSB xor Cout_MSB, Zero= NOR result, SLT uses subtract sign with overflow correction
- ALU flags 2
D. CORRECT Q2: Hardwired control uses combinational PLA faster but microprogrammed uses microcode
ROM flexible, ALU control 4 bits decoded from ALUOp and funct, PCSrc = Branch AND Zero, RegDst
selects rd vs rt, MemtoReg selects memory vs ALU.
Correct Answer: D
Rationale: Answer D is verified for Q2. This item evaluates CPU Organization: ALU 1-bit slice merges AND OR
ADD via MUX controlled by Operation; SUB uses inverted B and carry 1. Overflow signed detection is carry into
MSB XOR carry out, allowing trap or SLT correction. Ripple adder delay is sum of FA delays 1 stages, CLA
reduces to log via generate propagate. Single-cycle datapath critical path analysis shows load word longest
requiring instruction memory read, register read, ALU address calc, data memory read, writeback MUX. Multicycle
Page 4
