STUVIA EXAM LIBRARY
EXAMINATION DOCUMENT 2026/2027
D386 Computer Architecture and Operating
Systems Exam 3 2026/2027 - Memory Hierarchy
Cache Virtual Memory Review - 210 Q&A - A+
Graded - Latest Update This Year - Just
Released - Verified Solutions - Pass
Guaranteed
D386 Exam 3
Memory Hierarchy
A+ VERIFIED | WGU D386 | 210 Q&A
Computer Architecture Theme: SRAM DRAM Cache Virtual Memory Paging TLB - Gold accents #FFD700 on #0B1F4B
, TABLE OF CONTENTS - D386 Exam 3 Memory Hierarchy
Focus: Memory hierarchy pyramid, SRAM DRAM, cache mapping direct associative, replacement policies, write policies, virtual memory, pagi
1. Section 1: Memory Pyramid Foundations & Locality Principles (Q1-30)
30 Qs - Hierarchy cost-speed analysis
2. Section 2: SRAM Cell Design vs DRAM Capacitor Dynamics (Q31-60)
30 Qs - Refresh, density, volatility
3. Section 3: Direct-Mapped Cache Deconstruction Scenarios (Q61-75)
15 Qs - Index/Tag/Offset
4. Section 4: Set-Associative Way Selection & Trade-offs (Q76-90)
15 Qs - Associativity impact
5. Section 5: Fully Associative TLB-Style Cache Logic (Q91-110)
20 Qs - CAM search
6. Section 6: LRU LFU FIFO Random Replacement Wars (Q111-135)
25 Qs - Belady anomaly
7. Section 7: Write-Back Dirty Bits vs Write-Through Bandwidth (Q136-160)
25 Qs - Write allocate
8. Section 8: Virtual Memory Paging & Segmentation Mechanics (Q161-185)
25 Qs - VPN/VPO
9. Section 9: TLB Reach Hugepages & Effective Access Time Math (Q186-210)
25 Qs - AMAT EAT calc
,
, D386 Exam 3 - Memory Hierarchy | WGU Complete Exam Review 2026/2027 | A+ Graded
Q1. Scenario: A WGU D386 student profiles an application on a system where L1 cache is 128KB
with 2-cycle hit, main memory penalty is 120 cycles, and measured L1 hit rate is 97%. The student
wonders why memory is organized as a pyramid rather than flat DRAM. Which statement
correctly explains the pyramid organization and the calculated AMAT for this case?
A. The pyramid balances cost, capacity, and speed using locality; AMAT = hit_time + miss_rate × miss_penalty
= 5.6 cycles, justifying small fast levels atop large slow levels.
B. Hierarchy pyramid violates inclusion property and always increases AMAT compared to single-level
memory.
C. Pyramid exists because SSDs are faster than registers and cost is irrelevant to hierarchy design.
D. Flat memory of only DRAM would be faster because pyramid adds overhead; AMAT = 120 cycles always.
Rationale: The memory hierarchy pyramid is motivated by technology trade-offs: SRAM registers/L1 are fast (1-3 cycles) but
expensive and small, DRAM larger cheaper slower, disk largest cheapest slowest. Locality (temporal and spatial) means
90%+ accesses can be served by small fast layers, reducing AMAT dramatically compared to all-DRAM. Calculated AMAT
uses formula: AMAT = HitTime + MissRate×MissPenalty. With 97% hit rate, miss rate 3%, penalty 120, result 5.6 cycles
versus 120 cycles without cache. This validates pyramid design for WGU performance analysis tasks. | Correct: A. The
pyramid balances cost, capacity, and speed using locality; AMAT = hit_time + miss_rate × miss_penalty = 5.6 cycles,
justifying small fast levels atop large slow levels.
Q2. Scenario: A WGU D386 student profiles an application on a system where L1 cache is 64KB
with 2-cycle hit, main memory penalty is 80 cycles, and measured L1 hit rate is 92%. The student
wonders why memory is organized as a pyramid rather than flat DRAM. Which statement
correctly explains the pyramid organization and the calculated AMAT for this case?
A. Pyramid exists because SSDs are faster than registers and cost is irrelevant to hierarchy design.
B. Flat memory of only DRAM would be faster because pyramid adds overhead; AMAT = 80 cycles always.
C. The pyramid balances cost, capacity, and speed using locality; AMAT = hit_time + miss_rate × miss_penalty
= 8.4 cycles, justifying small fast levels atop large slow levels.
D. Hierarchy pyramid violates inclusion property and always increases AMAT compared to single-level
memory.
Rationale: The memory hierarchy pyramid is motivated by technology trade-offs: SRAM registers/L1 are fast (1-3 cycles) but
expensive and small, DRAM larger cheaper slower, disk largest cheapest slowest. Locality (temporal and spatial) means
90%+ accesses can be served by small fast layers, reducing AMAT dramatically compared to all-DRAM. Calculated AMAT
uses formula: AMAT = HitTime + MissRate×MissPenalty. With 92% hit rate, miss rate 8%, penalty 80, result 8.4 cycles versus
80 cycles without cache. This validates pyramid design for WGU performance analysis tasks. | Correct: C. The pyramid
balances cost, capacity, and speed using locality; AMAT = hit_time + miss_rate × miss_penalty = 8.4 cycles, justifying small
fast levels atop large slow levels.
EXAMINATION DOCUMENT 2026/2027
D386 Computer Architecture and Operating
Systems Exam 3 2026/2027 - Memory Hierarchy
Cache Virtual Memory Review - 210 Q&A - A+
Graded - Latest Update This Year - Just
Released - Verified Solutions - Pass
Guaranteed
D386 Exam 3
Memory Hierarchy
A+ VERIFIED | WGU D386 | 210 Q&A
Computer Architecture Theme: SRAM DRAM Cache Virtual Memory Paging TLB - Gold accents #FFD700 on #0B1F4B
, TABLE OF CONTENTS - D386 Exam 3 Memory Hierarchy
Focus: Memory hierarchy pyramid, SRAM DRAM, cache mapping direct associative, replacement policies, write policies, virtual memory, pagi
1. Section 1: Memory Pyramid Foundations & Locality Principles (Q1-30)
30 Qs - Hierarchy cost-speed analysis
2. Section 2: SRAM Cell Design vs DRAM Capacitor Dynamics (Q31-60)
30 Qs - Refresh, density, volatility
3. Section 3: Direct-Mapped Cache Deconstruction Scenarios (Q61-75)
15 Qs - Index/Tag/Offset
4. Section 4: Set-Associative Way Selection & Trade-offs (Q76-90)
15 Qs - Associativity impact
5. Section 5: Fully Associative TLB-Style Cache Logic (Q91-110)
20 Qs - CAM search
6. Section 6: LRU LFU FIFO Random Replacement Wars (Q111-135)
25 Qs - Belady anomaly
7. Section 7: Write-Back Dirty Bits vs Write-Through Bandwidth (Q136-160)
25 Qs - Write allocate
8. Section 8: Virtual Memory Paging & Segmentation Mechanics (Q161-185)
25 Qs - VPN/VPO
9. Section 9: TLB Reach Hugepages & Effective Access Time Math (Q186-210)
25 Qs - AMAT EAT calc
,
, D386 Exam 3 - Memory Hierarchy | WGU Complete Exam Review 2026/2027 | A+ Graded
Q1. Scenario: A WGU D386 student profiles an application on a system where L1 cache is 128KB
with 2-cycle hit, main memory penalty is 120 cycles, and measured L1 hit rate is 97%. The student
wonders why memory is organized as a pyramid rather than flat DRAM. Which statement
correctly explains the pyramid organization and the calculated AMAT for this case?
A. The pyramid balances cost, capacity, and speed using locality; AMAT = hit_time + miss_rate × miss_penalty
= 5.6 cycles, justifying small fast levels atop large slow levels.
B. Hierarchy pyramid violates inclusion property and always increases AMAT compared to single-level
memory.
C. Pyramid exists because SSDs are faster than registers and cost is irrelevant to hierarchy design.
D. Flat memory of only DRAM would be faster because pyramid adds overhead; AMAT = 120 cycles always.
Rationale: The memory hierarchy pyramid is motivated by technology trade-offs: SRAM registers/L1 are fast (1-3 cycles) but
expensive and small, DRAM larger cheaper slower, disk largest cheapest slowest. Locality (temporal and spatial) means
90%+ accesses can be served by small fast layers, reducing AMAT dramatically compared to all-DRAM. Calculated AMAT
uses formula: AMAT = HitTime + MissRate×MissPenalty. With 97% hit rate, miss rate 3%, penalty 120, result 5.6 cycles
versus 120 cycles without cache. This validates pyramid design for WGU performance analysis tasks. | Correct: A. The
pyramid balances cost, capacity, and speed using locality; AMAT = hit_time + miss_rate × miss_penalty = 5.6 cycles,
justifying small fast levels atop large slow levels.
Q2. Scenario: A WGU D386 student profiles an application on a system where L1 cache is 64KB
with 2-cycle hit, main memory penalty is 80 cycles, and measured L1 hit rate is 92%. The student
wonders why memory is organized as a pyramid rather than flat DRAM. Which statement
correctly explains the pyramid organization and the calculated AMAT for this case?
A. Pyramid exists because SSDs are faster than registers and cost is irrelevant to hierarchy design.
B. Flat memory of only DRAM would be faster because pyramid adds overhead; AMAT = 80 cycles always.
C. The pyramid balances cost, capacity, and speed using locality; AMAT = hit_time + miss_rate × miss_penalty
= 8.4 cycles, justifying small fast levels atop large slow levels.
D. Hierarchy pyramid violates inclusion property and always increases AMAT compared to single-level
memory.
Rationale: The memory hierarchy pyramid is motivated by technology trade-offs: SRAM registers/L1 are fast (1-3 cycles) but
expensive and small, DRAM larger cheaper slower, disk largest cheapest slowest. Locality (temporal and spatial) means
90%+ accesses can be served by small fast layers, reducing AMAT dramatically compared to all-DRAM. Calculated AMAT
uses formula: AMAT = HitTime + MissRate×MissPenalty. With 92% hit rate, miss rate 8%, penalty 80, result 8.4 cycles versus
80 cycles without cache. This validates pyramid design for WGU performance analysis tasks. | Correct: C. The pyramid
balances cost, capacity, and speed using locality; AMAT = hit_time + miss_rate × miss_penalty = 8.4 cycles, justifying small
fast levels atop large slow levels.
