CSE 230 Final Questions with Correct Answers (Grade A+)
Question 1: Select the hardware that is active during the Memory Access stage of the instruction cycle:
Data Memory Program Counter Instruction Memory Control Unit Register File ALU
Answer: Data Memory
Question 2: Stages of Instruction Cycle
Answer: Fetch Decode Execute Store
Question 3: Select the hardware that is active during the Fetch Stage of the instruction cycle: Register
File ALU Data Memory Program Counter Instruction Memory Control Unit
Answer: Program Counter Instruction Memory
Question 4: What is the maximum speedup (upper limit) of an N-stage pipelined processor? N/2 N N*N
4
Answer: N
Question 5: Which of the following are true about single cycle vs. pipelined processor designs? (Select
all that apply). Pipelined processors have decreased throughput compared to single-cycle designs. The
clock rate of single-cycle processors can be higher than that of pipelined designs. In a single cycle
design, a single instruction is executing in the processor during any single clock cycle. In a pipelined
design, the processor components are fully utilized, but by different instructions.
Answer: In a single cycle design, a single instruction is executing in the processor during any single clock
cycle. In a pipelined design, the processor components are fully utilized, but by different instructions.
Question 6: The speedup of a pipelined processor is due to the: Increased instruction count. Reduced
latency of executing each instruction. Reduced complexity of processor hardware. Increased
throughput.
Answer: Increased throughput.
Question 7: Which of the following must be added to a single-cycle processor in order to implement a
pipelined design? (Select all that apply) Modified Registers for simultaneous read/write. Hazard
Detection & Mitigation Hardware Additional RAM Additional Pipelining Instruction types. Pipeline
Registers
Answer: Modified Registers for simultaneous read/write. Hazard Detection & Mitigation Hardware Pipeline
Registers
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, Question 8: Where do we save the control signals for different instructions in a pipelined datapath? In
the 32 floating-point registers. In pipeline registers between the stages. In the 32 integer registers In the
stack.
Answer: In pipeline registers between the stages.
Question 9: Given the following code, what hazards occur? lw $s1, 0($s0) lw $s2, 4($s0) add $s3, $s1, $s2
sw $s3, 12($s0) lw $s4, 8($s0) add $s5, $s1, $s4 Structure Hazards Data Hazards None of these. Control
Hazards
Answer: Data Hazards
Question 10: A load instruction can cause a pipeline hazard because: It cannot cause a stall. The
memory write operation updates a memory location near the end of the pipeline The address of the next
instruction is unknown The memory read operation updates a register near the end of the pipeline Two
instructions use the same memory address
Answer: The memory read operation updates a register near the end of the pipeline
Question 11: Forwarding (bypassing) alone can completely avoid stall (bubble) caused by: Branching
Instructions All Instructions Store Instruction Load Instruction Arithmetic Instructions
Answer: Arithmetic Instructions
Question 12: Given the following code, what hazards occur? lw $s1, 0($s0) lw $s2, 4($s0) sw $s3, 12($s0)
lw $s4, 8($s0) add $s5, $s0, $s3 None of these. Data Hazards Structure Hazards Control Hazards
Answer: None of these.
Question 13: Which of the following techniques can reduce the effect of the hazards in this piece of code
(Select all that apply): lw $s1, 0($s0) lw $s2, 4($s0) add $s3, $s1, $s2 sw $s3, 12($s0) lw $s4, 8($s0) add
$s5, $s1, $s4 Overflow Handling Early Decision Forwarding Branch Prediction Answer Stall
Answer: Forwarding Answer Stall
Question 14: Which of the following describes static branch prediction? A history table is used to store
a single bit mapped to the branch instruction address, indicating that the branch was previously taken
or untaken. A history table is used to store multiple bits, mapped to the branch instruction address,
indicating the history of the branch behavior. A state machine is used to update the table. The next
instruction to load after a branch instruction is randomly chosen from instruction memory. Hardware
designer specifies to always predict a taken or untaken branch.
Answer: Hardware designer specifies to always predict a taken or untaken branch.
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Question 1: Select the hardware that is active during the Memory Access stage of the instruction cycle:
Data Memory Program Counter Instruction Memory Control Unit Register File ALU
Answer: Data Memory
Question 2: Stages of Instruction Cycle
Answer: Fetch Decode Execute Store
Question 3: Select the hardware that is active during the Fetch Stage of the instruction cycle: Register
File ALU Data Memory Program Counter Instruction Memory Control Unit
Answer: Program Counter Instruction Memory
Question 4: What is the maximum speedup (upper limit) of an N-stage pipelined processor? N/2 N N*N
4
Answer: N
Question 5: Which of the following are true about single cycle vs. pipelined processor designs? (Select
all that apply). Pipelined processors have decreased throughput compared to single-cycle designs. The
clock rate of single-cycle processors can be higher than that of pipelined designs. In a single cycle
design, a single instruction is executing in the processor during any single clock cycle. In a pipelined
design, the processor components are fully utilized, but by different instructions.
Answer: In a single cycle design, a single instruction is executing in the processor during any single clock
cycle. In a pipelined design, the processor components are fully utilized, but by different instructions.
Question 6: The speedup of a pipelined processor is due to the: Increased instruction count. Reduced
latency of executing each instruction. Reduced complexity of processor hardware. Increased
throughput.
Answer: Increased throughput.
Question 7: Which of the following must be added to a single-cycle processor in order to implement a
pipelined design? (Select all that apply) Modified Registers for simultaneous read/write. Hazard
Detection & Mitigation Hardware Additional RAM Additional Pipelining Instruction types. Pipeline
Registers
Answer: Modified Registers for simultaneous read/write. Hazard Detection & Mitigation Hardware Pipeline
Registers
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, Question 8: Where do we save the control signals for different instructions in a pipelined datapath? In
the 32 floating-point registers. In pipeline registers between the stages. In the 32 integer registers In the
stack.
Answer: In pipeline registers between the stages.
Question 9: Given the following code, what hazards occur? lw $s1, 0($s0) lw $s2, 4($s0) add $s3, $s1, $s2
sw $s3, 12($s0) lw $s4, 8($s0) add $s5, $s1, $s4 Structure Hazards Data Hazards None of these. Control
Hazards
Answer: Data Hazards
Question 10: A load instruction can cause a pipeline hazard because: It cannot cause a stall. The
memory write operation updates a memory location near the end of the pipeline The address of the next
instruction is unknown The memory read operation updates a register near the end of the pipeline Two
instructions use the same memory address
Answer: The memory read operation updates a register near the end of the pipeline
Question 11: Forwarding (bypassing) alone can completely avoid stall (bubble) caused by: Branching
Instructions All Instructions Store Instruction Load Instruction Arithmetic Instructions
Answer: Arithmetic Instructions
Question 12: Given the following code, what hazards occur? lw $s1, 0($s0) lw $s2, 4($s0) sw $s3, 12($s0)
lw $s4, 8($s0) add $s5, $s0, $s3 None of these. Data Hazards Structure Hazards Control Hazards
Answer: None of these.
Question 13: Which of the following techniques can reduce the effect of the hazards in this piece of code
(Select all that apply): lw $s1, 0($s0) lw $s2, 4($s0) add $s3, $s1, $s2 sw $s3, 12($s0) lw $s4, 8($s0) add
$s5, $s1, $s4 Overflow Handling Early Decision Forwarding Branch Prediction Answer Stall
Answer: Forwarding Answer Stall
Question 14: Which of the following describes static branch prediction? A history table is used to store
a single bit mapped to the branch instruction address, indicating that the branch was previously taken
or untaken. A history table is used to store multiple bits, mapped to the branch instruction address,
indicating the history of the branch behavior. A state machine is used to update the table. The next
instruction to load after a branch instruction is randomly chosen from instruction memory. Hardware
designer specifies to always predict a taken or untaken branch.
Answer: Hardware designer specifies to always predict a taken or untaken branch.
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