ITE 221 - PC Hardware & O/C
Architecture - Exam 2 UPDATED
ACTUAL QUESTIONS AND CORRECT
ANSWERS
L1 or level one - CORRECT ANSWER A(n) _____ cache is generally implemented on the
same chip as the CPU.
cache - CORRECT ANSWER A(n) _____ is an area of fast memory where data held in a
storage device is prefetched in anticipation of future requests for the data.
cache swap - CORRECT ANSWER A cache controller is a hardware device that initiates a(n)
_____ when it detects a cache miss.
control bus - CORRECT ANSWER The _____ transmits command, timing, and status signals
between devices in a computer system and carries interrupts, command responses, status codes, and
similar messages.
stack pointer - CORRECT ANSWER The _____ is a special-purpose register that always
points to the next empty address in the stack.
machine state - CORRECT ANSWER The set of register values stored in the stack while
processing an interrupt is also called the _____.
interrupt handler - CORRECT ANSWER A(n) _____ is a program stored in a separate part of
primary storage to process a specific interrupt.
stack - CORRECT ANSWER During interrupt processing, register values of a suspended
process are held on the _____.
memory bus - CORRECT ANSWER The _____ has a much higher data transfer rate than the
system bus because of its shorter length, higher clock rate, and large number of parallel
communication lines.
, cache controller - CORRECT ANSWER A(n) _____ is a special-purpose processor dedicated
to managing cache content.
address bus - CORRECT ANSWER The _____ transmits a memory address when primary
storage is the sending or receiving device.
linear address space - CORRECT ANSWER The CPU and bus normally view and storage
device as a(n) _____, ignoring the device's physical storage organization.
logical accesses - CORRECT ANSWER Part of a device controller's function is to translate
_____ into physical accesses.
DMA - CORRECT ANSWER A(n) _____ controller assumes the role of bus master for all
transfers between memory and other storage or I/O devices, leaving the CPU free to execute
computation and data movement instructions.
channel - CORRECT ANSWER A(n) _____ is a high-capacity device controller used in
mainframe computers.
cache hit - CORRECT ANSWER When a read operation accesses data already contained in the
cache, it's called a(n) _____.
bus protocol - CORRECT ANSWER The _____ defines the format, content, and timing of
data, memory addresses, and control messages sent across the bus.
multicore - CORRECT ANSWER In _____ architecture, multiple CPUs and cache memory are
embedded on a single chip.
scaling up - CORRECT ANSWER The term _____ describes methods of increasing processing
and other computer system power by using larger and more powerful computers.
Storage - CORRECT ANSWER Examples of a(n) _____ bus include SATA and SCSI.
Architecture - Exam 2 UPDATED
ACTUAL QUESTIONS AND CORRECT
ANSWERS
L1 or level one - CORRECT ANSWER A(n) _____ cache is generally implemented on the
same chip as the CPU.
cache - CORRECT ANSWER A(n) _____ is an area of fast memory where data held in a
storage device is prefetched in anticipation of future requests for the data.
cache swap - CORRECT ANSWER A cache controller is a hardware device that initiates a(n)
_____ when it detects a cache miss.
control bus - CORRECT ANSWER The _____ transmits command, timing, and status signals
between devices in a computer system and carries interrupts, command responses, status codes, and
similar messages.
stack pointer - CORRECT ANSWER The _____ is a special-purpose register that always
points to the next empty address in the stack.
machine state - CORRECT ANSWER The set of register values stored in the stack while
processing an interrupt is also called the _____.
interrupt handler - CORRECT ANSWER A(n) _____ is a program stored in a separate part of
primary storage to process a specific interrupt.
stack - CORRECT ANSWER During interrupt processing, register values of a suspended
process are held on the _____.
memory bus - CORRECT ANSWER The _____ has a much higher data transfer rate than the
system bus because of its shorter length, higher clock rate, and large number of parallel
communication lines.
, cache controller - CORRECT ANSWER A(n) _____ is a special-purpose processor dedicated
to managing cache content.
address bus - CORRECT ANSWER The _____ transmits a memory address when primary
storage is the sending or receiving device.
linear address space - CORRECT ANSWER The CPU and bus normally view and storage
device as a(n) _____, ignoring the device's physical storage organization.
logical accesses - CORRECT ANSWER Part of a device controller's function is to translate
_____ into physical accesses.
DMA - CORRECT ANSWER A(n) _____ controller assumes the role of bus master for all
transfers between memory and other storage or I/O devices, leaving the CPU free to execute
computation and data movement instructions.
channel - CORRECT ANSWER A(n) _____ is a high-capacity device controller used in
mainframe computers.
cache hit - CORRECT ANSWER When a read operation accesses data already contained in the
cache, it's called a(n) _____.
bus protocol - CORRECT ANSWER The _____ defines the format, content, and timing of
data, memory addresses, and control messages sent across the bus.
multicore - CORRECT ANSWER In _____ architecture, multiple CPUs and cache memory are
embedded on a single chip.
scaling up - CORRECT ANSWER The term _____ describes methods of increasing processing
and other computer system power by using larger and more powerful computers.
Storage - CORRECT ANSWER Examples of a(n) _____ bus include SATA and SCSI.
