QUESTIONS AND ANSWERS | 2026
UPDATE | 100% CORRECT - ACE.
140 Questions with Answers and Detailed Rationales
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EL 5753 MODULE 1 QUIZ | QUESTIONS AND ANSWERS | 2026 UPDATE | 100% CORRECT - ACE.. It
contains 140 carefully selected questions that reflect the most current exam content and testing strategies. Each
question is accompanied by a correct answer and a detailed rationale that explains the underlying
pathophysiology, pharmacology, or clinical reasoning.
Self-Assessment – Test your knowledge and Exam Preparation – Familiarize yourself with the
identify areas requiring further question format and content
study areas
Concept Reinforcement – Deepen your Confidence Building – Develop test-taking
understanding through strategies and reduce
evidence-based exam anxiety
rationales
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Review Summary 140 Questions
Foundations - Application - EL 5753 Module 1 AND 2026 Update 100 Correct - ACE Electrical Engineering
/ Embedded Systems Graduate
All answers with rationales
,Table of Contents
Content Area Questions Key Topics
Introduction TO Leadership 1-24 System, Execution TIME, Period, Distributed, Real-time
AND Management Theories
Ethical AND Legal Issues IN 25-48 Project, Leadership, Context, System, Model
Nursing Leadership
Healthcare Policy AND 49-72 Context, System, Network, Probability, Control
Advocacy
Quality Improvement AND 73-96 System, Describes, Design, Primary, Real-time
Patient Safety
Communication AND 97-120 System, Application, Particle, Engineer, Network
Interprofessional
Collaboration
Human Resource 121-140 System S, Design, Randomized, Trial, Transfer Function
Management AND Staffing
TOTAL 140 All questions include answers and detailed rationales
,Section A - Introduction TO Leadership AND Management
Theories
Q1.
In a deeply embedded system with a single-core processor, a periodic task set is
scheduled using Rate Monotonic Scheduling (RMS). Task T1 has period 50ms and
execution time 10ms; T2 has period 100ms and execution time 25ms; T3 has period 150ms
and execution time 30ms. The system also has a sporadic interrupt handler with
worst-case execution time 5ms and minimum inter-arrival time 200ms. Which statement
best assesses schedulability?
A. The task set is schedulable because the B. The task set is schedulable if the interrupt
total utilization is 0.75, which is below the handler is treated as a periodic task with
RM bound of 0.779 for three tasks. period 200ms and the RM bound is
recalculated for four tasks.
C. The task set is not schedulable because D. The task set is not schedulable because
the interrupt handler adds 5ms of blocking the RM bound for three tasks is 0.779 and
time, pushing the utilization over the bound. the total utilization is 0.75, but the interrupt
handler makes the effective utilization 0.775,
still below the bound, yet priority inversion
causes a missed deadline.
Correct: B - The task set is schedulable if the interrupt handler is treated as a periodic task
with period 200ms and the RM bound is recalculated for four tasks.
Rationale:The sporadic interrupt handler must be accounted for in schedulability analysis.
Treating it as a periodic task with its minimum inter-arrival time (200ms) and including it in the
RM utilization test yields a total utilization of 0.75 + 0.025 = 0.775, which is below the RM
bound for four tasks (0.756). However, the question asks which statement best assesses
schedulability; option B correctly recognizes the need to include the handler as a periodic
task. Option A ignores the handler, C incorrectly assumes blocking, and D miscomputes the
bound.
Q2.
In a heterogeneous multicore system with a Cortex-M7 (with caches) and a Cortex-M0+ (no
cache), a hard real-time task is partitioned. Which memory architecture consideration is
most critical for guaranteeing worst-case execution time (WCET) predictability?
A. Use cache locking on the M7 to make B. Place all time-critical code and data in
WCET analysis tractable and deterministic. tightly coupled memory (TCM) on both
cores.
C. Disable interrupts on both cores to D. Implement a cache coherence protocol to
prevent cache pollution. maintain data consistency between cores.
Page 3
, Section A - Introduction TO Leadership AND Management Theories
Correct: A - Use cache locking on the M7 to make WCET analysis tractable and
deterministic.
Rationale:Cache locking on the M7 makes WCET analysis feasible by eliminating cache
miss variability. TCM is also deterministic but may be limited in size; option A directly
addresses the predictability of the cached core. Disabling interrupts is not practical, and
cache coherence is unnecessary for independent tasks. Option B is a partial solution but not
the most critical for WCET prediction.
Q3.
In a mixed-criticality system using ARINC 653 partitioning, a partition is assigned a budget
of 20ms every 50ms period. The partition contains two tasks: one with a deadline of 25ms
and one with a deadline of 45ms. Which scheduling policy within the partition best
ensures both deadlines are met while maintaining temporal isolation?
A. Use fixed-priority preemptive scheduling B. Use round-robin scheduling with a time
with the shorter deadline task at higher slice of 10ms per task.
priority.
C. Use earliest deadline first (EDF) D. Use a two-level hierarchical scheduler
scheduling within the partition. where the partition receives its budget and
tasks are scheduled by a rate monotonic
scheduler.
Correct: C - Use earliest deadline first (EDF) scheduling within the partition.
Rationale:EDF is optimal for preemptive uniprocessor scheduling and will meet all deadlines
if the total utilization is 1. Within the partition, the budget is 20ms per 50ms, so utilization is
0.4. Both tasks can be scheduled by EDF. Fixed-priority may fail due to priority inversion,
round-robin may not meet the 25ms deadline, and hierarchical scheduling adds overhead
without benefit.
Q4.
A design team is implementing a digital filter on an FPGA. The filter requires 256
multiply-accumulate operations per sample. The system clock is 100 MHz, and the sample
rate is 48 kHz. Which implementation strategy minimizes power while meeting real-time
constraints?
A. Use a single MAC unit with B. Use a fully parallel array of 256 MAC
time-multiplexing, since the required units to minimize latency.
throughput is low.
C. Use a systolic array with 16 MAC units D. Use a general-purpose DSP processor
and pipeline registers to balance area and with SIMD instructions to reduce design
speed. time.
Correct: C - Use a systolic array with 16 MAC units and pipeline registers to balance area
and speed.
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