CS 6290 High Performance Computer
Architecture Exam Practice Questions
And Correct Answers (Verified Answers)
Plus Rationale 2027 Q&A| Instant
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1. In a modern superscalar processor, which statement most accurately
describes the primary purpose of exploiting instruction-level
parallelism (ILP)?
A. To increase the number of operating-system processes that can
execute simultaneously
B. To allow multiple independent instructions from a single sequential
instruction stream to execute concurrently when hardware resources
permit
C. To guarantee that every instruction completes in exactly one clock
cycle
D. To eliminate the need for cache memory
Answer: B
The purpose of ILP is to identify and execute independent instructions
concurrently, allowing a processor to achieve higher throughput than a
strictly sequential pipeline would provide. The hardware must nevertheless
preserve the architectural behavior of the original program.
, 2. A processor has a four-wide issue width but frequently achieves an
average issue rate of only 1.5 instructions per cycle. Which factor
could most directly explain this discrepancy?
A. The processor's clock frequency is necessarily too low
B. The program contains insufficient independent instructions, causing
instruction-level parallelism to be underutilized
C. The processor must have a larger L1 cache
D. The processor cannot contain branch prediction hardware
Answer: B
Issue width specifies the maximum number of instructions that can
potentially be dispatched or issued in a cycle; it does not guarantee that
many instructions will always be available or independent. Dependencies,
branches, cache misses, and resource conflicts can all reduce actual
utilization.
3. Consider the dependence chain ADD R1,R2,R3 followed immediately
by SUB R4,R1,R5. What type of dependence exists between the two
instructions, and why is it important for instruction scheduling?
A. Write-after-write dependence, because both instructions modify
registers
B. Write-after-read dependence, because the second instruction
writes R1
C. Read-after-write dependence, because the second instruction
requires the value produced by the first
D. Control dependence, because both instructions are in the same
basic block
Answer: C
The first instruction writes R1, and the second instruction reads R1,
creating a read-after-write (RAW) dependence. The second instruction
cannot obtain the correct operand until the first instruction has produced
it.
, 4. Which architectural technique most directly allows instructions to
execute out of program order while still preserving precise
architectural state at retirement?
A. Direct-mapped caching
B. A reorder buffer
C. Static branch prediction
D. A write-through cache
Answer: B
A reorder buffer tracks dynamically executed instructions and allows them
to execute when their operands are ready while requiring them to retire in
program order. This enables out-of-order execution while preserving
precise exceptions and the appearance of sequential execution.
5. A processor encounters the following sequence: instruction I1
produces a value, I2 depends on I1, and I3 is independent of both. In
an out-of-order processor, what is the principal advantage of allowing
I3 to execute before I2?
A. It eliminates the dependence between I1 and I2
B. It allows otherwise unused execution resources to perform useful
work while I2 waits for I1
C. It guarantees that I2 will never execute
D. It changes the program's architectural semantics
Answer: B
Out-of-order execution exploits available instruction-level parallelism by
allowing independent instructions to proceed while dependent instructions
wait. This can improve functional-unit utilization and overall throughput
without changing program semantics.
6. What is the primary role of register renaming in a dynamically
scheduled processor?
A. Increasing the number of cache lines in the L1 cache
B. Eliminating false dependencies caused by reuse of architectural
, register names
C. Eliminating all true data dependencies
D. Increasing virtual-memory capacity
Answer: B
Register renaming maps architectural registers to a larger set of physical
registers. This removes false WAR and WAW dependencies arising from
register-name reuse while preserving true RAW dependencies.
7. Which situation represents a write-after-write (WAW) dependence?
A. Instruction A reads R1 after instruction B writes R1
B. Instruction A writes R1 and a later instruction B writes R1
C. Instruction A writes R1 and a later instruction B reads R2
D. Two instructions access different memory locations
Answer: B
A WAW dependence occurs when two instructions write the same
destination, creating an ordering requirement for the final value. Register
renaming can eliminate this false dependence in an out-of-order processor.
8. Why is branch prediction particularly important in a deeply pipelined
superscalar processor?
A. A mispredicted branch can require the processor to discard many
speculatively fetched and executed instructions
B. Branch prediction eliminates all data dependencies
C. Branch prediction increases DRAM capacity
D. Branch prediction guarantees that every branch is predicted
correctly
Answer: A
The deeper and wider the pipeline, the greater the potential amount of
work performed after an unresolved branch. A misprediction therefore
causes a larger recovery penalty because incorrect speculative work must
be discarded.
Architecture Exam Practice Questions
And Correct Answers (Verified Answers)
Plus Rationale 2027 Q&A| Instant
Download Pdf.
1. In a modern superscalar processor, which statement most accurately
describes the primary purpose of exploiting instruction-level
parallelism (ILP)?
A. To increase the number of operating-system processes that can
execute simultaneously
B. To allow multiple independent instructions from a single sequential
instruction stream to execute concurrently when hardware resources
permit
C. To guarantee that every instruction completes in exactly one clock
cycle
D. To eliminate the need for cache memory
Answer: B
The purpose of ILP is to identify and execute independent instructions
concurrently, allowing a processor to achieve higher throughput than a
strictly sequential pipeline would provide. The hardware must nevertheless
preserve the architectural behavior of the original program.
, 2. A processor has a four-wide issue width but frequently achieves an
average issue rate of only 1.5 instructions per cycle. Which factor
could most directly explain this discrepancy?
A. The processor's clock frequency is necessarily too low
B. The program contains insufficient independent instructions, causing
instruction-level parallelism to be underutilized
C. The processor must have a larger L1 cache
D. The processor cannot contain branch prediction hardware
Answer: B
Issue width specifies the maximum number of instructions that can
potentially be dispatched or issued in a cycle; it does not guarantee that
many instructions will always be available or independent. Dependencies,
branches, cache misses, and resource conflicts can all reduce actual
utilization.
3. Consider the dependence chain ADD R1,R2,R3 followed immediately
by SUB R4,R1,R5. What type of dependence exists between the two
instructions, and why is it important for instruction scheduling?
A. Write-after-write dependence, because both instructions modify
registers
B. Write-after-read dependence, because the second instruction
writes R1
C. Read-after-write dependence, because the second instruction
requires the value produced by the first
D. Control dependence, because both instructions are in the same
basic block
Answer: C
The first instruction writes R1, and the second instruction reads R1,
creating a read-after-write (RAW) dependence. The second instruction
cannot obtain the correct operand until the first instruction has produced
it.
, 4. Which architectural technique most directly allows instructions to
execute out of program order while still preserving precise
architectural state at retirement?
A. Direct-mapped caching
B. A reorder buffer
C. Static branch prediction
D. A write-through cache
Answer: B
A reorder buffer tracks dynamically executed instructions and allows them
to execute when their operands are ready while requiring them to retire in
program order. This enables out-of-order execution while preserving
precise exceptions and the appearance of sequential execution.
5. A processor encounters the following sequence: instruction I1
produces a value, I2 depends on I1, and I3 is independent of both. In
an out-of-order processor, what is the principal advantage of allowing
I3 to execute before I2?
A. It eliminates the dependence between I1 and I2
B. It allows otherwise unused execution resources to perform useful
work while I2 waits for I1
C. It guarantees that I2 will never execute
D. It changes the program's architectural semantics
Answer: B
Out-of-order execution exploits available instruction-level parallelism by
allowing independent instructions to proceed while dependent instructions
wait. This can improve functional-unit utilization and overall throughput
without changing program semantics.
6. What is the primary role of register renaming in a dynamically
scheduled processor?
A. Increasing the number of cache lines in the L1 cache
B. Eliminating false dependencies caused by reuse of architectural
, register names
C. Eliminating all true data dependencies
D. Increasing virtual-memory capacity
Answer: B
Register renaming maps architectural registers to a larger set of physical
registers. This removes false WAR and WAW dependencies arising from
register-name reuse while preserving true RAW dependencies.
7. Which situation represents a write-after-write (WAW) dependence?
A. Instruction A reads R1 after instruction B writes R1
B. Instruction A writes R1 and a later instruction B writes R1
C. Instruction A writes R1 and a later instruction B reads R2
D. Two instructions access different memory locations
Answer: B
A WAW dependence occurs when two instructions write the same
destination, creating an ordering requirement for the final value. Register
renaming can eliminate this false dependence in an out-of-order processor.
8. Why is branch prediction particularly important in a deeply pipelined
superscalar processor?
A. A mispredicted branch can require the processor to discard many
speculatively fetched and executed instructions
B. Branch prediction eliminates all data dependencies
C. Branch prediction increases DRAM capacity
D. Branch prediction guarantees that every branch is predicted
correctly
Answer: A
The deeper and wider the pipeline, the greater the potential amount of
work performed after an unresolved branch. A misprediction therefore
causes a larger recovery penalty because incorrect speculative work must
be discarded.
