ADVANCED COMPUTER
ORGANIZATION AND ARCHITECTURE -
TEST 3 QUESTIONS AND ANSWERS
1. In a 5-stage RISC pipeline (IF, ID, EX, MEM, WB), which hazard occurs when a required
resource is busy?
A. Data Hazard
B. Control Hazard
C. Structural Hazard
D. Branch Hazard
Answer: C
Conceptual Explanation: A structural hazard occurs when the hardware cannot support
all possible combinations of instructions in the same clock cycle due to resource conflicts.
2. Which of the following techniques is primarily used to resolve RAW (Read After Write)
hazards in a pipeline?
A. Data Forwarding (Bypassing)
B. Register Renaming
,C. Branch Prediction
D. Speculative Execution
Answer: A
Conceptual Explanation: Data forwarding allows the result of an operation to be used by a
subsequent instruction before it is written back to the register file.
3. Amdahl’s Law states that the speedup of a system is limited by:
A. The sequential fraction of the task
B. The number of processors in the system
C. The clock frequency of the CPU
D. The size of the cache memory
Answer: A
Conceptual Explanation: The speedup is capped by 1/s, where s is the serial portion of
the execution that cannot be parallelized.
4. In the context of Tomasulo’s algorithm, what is the purpose of Reservation Stations?
A. To store instructions before they are decoded
B. To buffer operands for functional units and implement register renaming
C. To manage the instruction fetch queue
D. To store the final results for the Write Back stage
, Answer: B
Conceptual Explanation: Reservation stations hold instructions and their operands,
effectively renaming registers to avoid WAW and WAR hazards.
5. Which cache mapping technique allows a block of main memory to be placed in any line of
the cache?
A. Direct Mapping
B. Set-Associative Mapping
C. Sector Mapping
D. Fully Associative Mapping
Answer: D
Conceptual Explanation: Fully associative mapping provides the most flexibility, allowing
any main memory block to reside in any cache slot.
6. What is the ‘Victim Cache’ designed to reduce?
A. Conflict misses
B. Capacity misses
C. Compulsory misses
D. Coherence misses
Answer: A
ORGANIZATION AND ARCHITECTURE -
TEST 3 QUESTIONS AND ANSWERS
1. In a 5-stage RISC pipeline (IF, ID, EX, MEM, WB), which hazard occurs when a required
resource is busy?
A. Data Hazard
B. Control Hazard
C. Structural Hazard
D. Branch Hazard
Answer: C
Conceptual Explanation: A structural hazard occurs when the hardware cannot support
all possible combinations of instructions in the same clock cycle due to resource conflicts.
2. Which of the following techniques is primarily used to resolve RAW (Read After Write)
hazards in a pipeline?
A. Data Forwarding (Bypassing)
B. Register Renaming
,C. Branch Prediction
D. Speculative Execution
Answer: A
Conceptual Explanation: Data forwarding allows the result of an operation to be used by a
subsequent instruction before it is written back to the register file.
3. Amdahl’s Law states that the speedup of a system is limited by:
A. The sequential fraction of the task
B. The number of processors in the system
C. The clock frequency of the CPU
D. The size of the cache memory
Answer: A
Conceptual Explanation: The speedup is capped by 1/s, where s is the serial portion of
the execution that cannot be parallelized.
4. In the context of Tomasulo’s algorithm, what is the purpose of Reservation Stations?
A. To store instructions before they are decoded
B. To buffer operands for functional units and implement register renaming
C. To manage the instruction fetch queue
D. To store the final results for the Write Back stage
, Answer: B
Conceptual Explanation: Reservation stations hold instructions and their operands,
effectively renaming registers to avoid WAW and WAR hazards.
5. Which cache mapping technique allows a block of main memory to be placed in any line of
the cache?
A. Direct Mapping
B. Set-Associative Mapping
C. Sector Mapping
D. Fully Associative Mapping
Answer: D
Conceptual Explanation: Fully associative mapping provides the most flexibility, allowing
any main memory block to reside in any cache slot.
6. What is the ‘Victim Cache’ designed to reduce?
A. Conflict misses
B. Capacity misses
C. Compulsory misses
D. Coherence misses
Answer: A
