COMPUTER ORGANIZATION AND
ARCHITECTURE (COA) ADVANCED
ASSESSMENT QUESTIONS AND
ANSWERS
1. In a 4-way set-associative cache with a total capacity of 64 KB and a block size of 64 bytes,
how many bits are used for the ‘index’ field in a 32-bit memory address?
A. 8 bits
B. 10 bits
C. 12 bits
D. 14 bits
Answer: A
Conceptual Explanation: Total blocks = 64KB / 64B = 1024. Number of sets = =
256. Index bits = log2(256) = 8.
2. Which of the following hazards occurs when the pipeline must be stalled because the
hardware cannot support all possible combinations of instructions in the same clock cycle?
A. Data Hazard
B. Control Hazard
,C. Branch Hazard
D. Structural Hazard
Answer: D
Conceptual Explanation: Structural hazards arise from resource conflicts where the
hardware cannot support all instructions in the pipeline simultaneously.
3. In the IEEE 754 single-precision floating-point format, what is the bias value added to the
exponent?
A. 128
B. 127
C. 1023
D. 255
Answer: B
Conceptual Explanation: For single precision (32-bit), the exponent bias is 127. For
double precision (64-bit), it is 1023.
4. Using Booth’s algorithm for multiplication of signed binary numbers, what is the bit
operation performed when the current multiplier bit is 0 and the previous bit is 1 (01)?
A. Double the multiplicand and add
B. Subtract multiplicand from the product
C. No arithmetic operation, just shift
, D. Add multiplicand to the product
Answer: D
Conceptual Explanation: In Booth’s algorithm, the pair 01 signifies the end of a string of
1s, requiring an addition of the multiplicand.
5. Which cache write policy updates both the cache and the main memory simultaneously
every time a write occurs?
A. Write-back
B. Write-around
C. Write-allocate
D. Write-through
Answer: D
Conceptual Explanation: Write-through ensures consistency by updating both the cache
and the backing store (memory) at the same time.
6. In a CPU with a 5-stage pipeline (IF, ID, EX, MEM, WB), a ‘Read After Write’ (RAW)
dependency usually causes which type of hazard?
A. Structural Hazard
B. Control Hazard
C. Data Hazard
D. Instruction Hazard
ARCHITECTURE (COA) ADVANCED
ASSESSMENT QUESTIONS AND
ANSWERS
1. In a 4-way set-associative cache with a total capacity of 64 KB and a block size of 64 bytes,
how many bits are used for the ‘index’ field in a 32-bit memory address?
A. 8 bits
B. 10 bits
C. 12 bits
D. 14 bits
Answer: A
Conceptual Explanation: Total blocks = 64KB / 64B = 1024. Number of sets = =
256. Index bits = log2(256) = 8.
2. Which of the following hazards occurs when the pipeline must be stalled because the
hardware cannot support all possible combinations of instructions in the same clock cycle?
A. Data Hazard
B. Control Hazard
,C. Branch Hazard
D. Structural Hazard
Answer: D
Conceptual Explanation: Structural hazards arise from resource conflicts where the
hardware cannot support all instructions in the pipeline simultaneously.
3. In the IEEE 754 single-precision floating-point format, what is the bias value added to the
exponent?
A. 128
B. 127
C. 1023
D. 255
Answer: B
Conceptual Explanation: For single precision (32-bit), the exponent bias is 127. For
double precision (64-bit), it is 1023.
4. Using Booth’s algorithm for multiplication of signed binary numbers, what is the bit
operation performed when the current multiplier bit is 0 and the previous bit is 1 (01)?
A. Double the multiplicand and add
B. Subtract multiplicand from the product
C. No arithmetic operation, just shift
, D. Add multiplicand to the product
Answer: D
Conceptual Explanation: In Booth’s algorithm, the pair 01 signifies the end of a string of
1s, requiring an addition of the multiplicand.
5. Which cache write policy updates both the cache and the main memory simultaneously
every time a write occurs?
A. Write-back
B. Write-around
C. Write-allocate
D. Write-through
Answer: D
Conceptual Explanation: Write-through ensures consistency by updating both the cache
and the backing store (memory) at the same time.
6. In a CPU with a 5-stage pipeline (IF, ID, EX, MEM, WB), a ‘Read After Write’ (RAW)
dependency usually causes which type of hazard?
A. Structural Hazard
B. Control Hazard
C. Data Hazard
D. Instruction Hazard
