COA ACTUAL TEST 1 QUESTIONS AND
ANSWERS. VERIFIED
1. Which of the following describes the ‘write-through’ policy in cache memory?
A. Data is updated in the cache and only written to main memory when the block is
replaced.
B. Data is written only to main memory, bypassing the cache entirely.
C. Data is written to both the cache and the main memory simultaneously.
D. Data is written to a buffer and then asynchronously moved to the main memory.
Answer: C
Conceptual Explanation: In a write-through policy, every write operation to the cache is
also performed on the main memory to ensure consistency.
2. In computer architecture, what does Amdahl’s Law primarily measure?
A. The power consumption of multi-core processors.
B. The maximum throughput of a pipeline.
C. The theoretical speedup in latency of the execution of a task at fixed workload.
,D. The reliability of a memory system.
Answer: C
Conceptual Explanation: Amdahl’s Law provides the theoretical speedup in latency of the
execution of a task at fixed workload that can be expected of a system whose resources are
improved.
3. Which hazard occurs when an instruction depends on the result of a previous instruction
that is still in the pipeline?
A. Structural hazard
B. Data hazard
C. Control hazard
D. Branch hazard
Answer: B
Conceptual Explanation: Data hazards arise when an instruction depends on the results
of a previous instruction in a way that is exposed by the overlapping of instructions in the
pipeline.
4. A 4-way set-associative cache has a total size of 16KB and a block size of 64 bytes. How
many sets are in the cache?
A. 1024
B. 256
, C. 128
D. 64
Answer: D
Conceptual Explanation: Total blocks = 16KB / 64B = 256. Number of sets = Total blocks
/ Associativity = = 64.
5. Which addressing mode uses the value in a register as the address of the operand?
A. Register Indirect
B. Immediate
C. Register Direct
D. Displacement
Answer: A
Conceptual Explanation: In Register Indirect addressing mode, the register contains the
effective address of the operand rather than the operand itself.
6. What is the purpose of a Translation Lookaside Buffer (TLB)?
A. To speed up virtual-to-physical address translation.
B. To store frequently used instructions.
C. To act as a buffer for DMA transfers.
D. To manage hardware interrupts.
ANSWERS. VERIFIED
1. Which of the following describes the ‘write-through’ policy in cache memory?
A. Data is updated in the cache and only written to main memory when the block is
replaced.
B. Data is written only to main memory, bypassing the cache entirely.
C. Data is written to both the cache and the main memory simultaneously.
D. Data is written to a buffer and then asynchronously moved to the main memory.
Answer: C
Conceptual Explanation: In a write-through policy, every write operation to the cache is
also performed on the main memory to ensure consistency.
2. In computer architecture, what does Amdahl’s Law primarily measure?
A. The power consumption of multi-core processors.
B. The maximum throughput of a pipeline.
C. The theoretical speedup in latency of the execution of a task at fixed workload.
,D. The reliability of a memory system.
Answer: C
Conceptual Explanation: Amdahl’s Law provides the theoretical speedup in latency of the
execution of a task at fixed workload that can be expected of a system whose resources are
improved.
3. Which hazard occurs when an instruction depends on the result of a previous instruction
that is still in the pipeline?
A. Structural hazard
B. Data hazard
C. Control hazard
D. Branch hazard
Answer: B
Conceptual Explanation: Data hazards arise when an instruction depends on the results
of a previous instruction in a way that is exposed by the overlapping of instructions in the
pipeline.
4. A 4-way set-associative cache has a total size of 16KB and a block size of 64 bytes. How
many sets are in the cache?
A. 1024
B. 256
, C. 128
D. 64
Answer: D
Conceptual Explanation: Total blocks = 16KB / 64B = 256. Number of sets = Total blocks
/ Associativity = = 64.
5. Which addressing mode uses the value in a register as the address of the operand?
A. Register Indirect
B. Immediate
C. Register Direct
D. Displacement
Answer: A
Conceptual Explanation: In Register Indirect addressing mode, the register contains the
effective address of the operand rather than the operand itself.
6. What is the purpose of a Translation Lookaside Buffer (TLB)?
A. To speed up virtual-to-physical address translation.
B. To store frequently used instructions.
C. To act as a buffer for DMA transfers.
D. To manage hardware interrupts.
