BTCS-310 Computer Organization Final Exam | Complete
Practice QUESTIONs, Verified Answers & Detailed Explanations
(2026/2027)
QUESTION 1
What is the 8-bit two's complement representation of the decimal
number −45?
A. 11010011
B. 10101100
C. 11010100
D. 00101101
Correct Answer: A. 11010011
Detailed Rationale: First, find the binary representation of +45, which
is 00101101. Next, invert all the bits (one's complement) to get
11010010. Finally, add 1 to the least significant bit: 11010010 + 1 =
11010011.
QUESTION 2
In the IEEE 754 single-precision (32-bit) floating-point format, how
many bits are allocated for the exponent?
A. 8 bits
B. 11 bits
C. 23 bits
D. 32 bits
,Correct Answer: A. 8 bits
Detailed Rationale: The IEEE 754 single-precision format consists of 1
sign bit, 8 exponent bits, and 23 fraction/mantissa bits, totaling 32 bits.
(Double-precision uses 11 bits for the exponent).
QUESTION 3
Which logic gate is universally known as a "universal gate" because any
Boolean function can be implemented using it alone?
A. AND gate
B. OR gate
C. NAND gate
D. XOR gate
Correct Answer: C. NAND gate
Detailed Rationale: Both NAND and NOR gates are universal gates. Any
logical function or gate (AND, OR, NOT) can be constructed using
exclusively NAND gates or exclusively NOR gates.
QUESTION 4
A multiplexer with 16 data inputs requires how many selection lines?
A. 2
B. 3
C. 4
D. 5
Correct Answer: C. 4
,Detailed Rationale: The relationship between data inputs (𝑁) and
selection lines (𝑠) in a multiplexer is 𝑁 = 2𝑠 . For 16 inputs, 2𝑠 = 16,
which means 𝑠 = 4 selection lines are required.
QUESTION 5
Which flip-flop configuration is specifically designed to eliminate the
race-around condition present in standard level-triggered JK flip-flops?
A. SR flip-flop
B. D flip-flop
C. Master-Slave JK flip-flop
D. T flip-flop
Correct Answer: C. Master-Slave JK flip-flop
Detailed Rationale: A Master-Slave flip-flop consists of two cascaded
flip-flops (master and slave) driven by complementary clock pulses. This
prevents the output from changing state while the inputs are still active
during the same clock pulse, avoiding the race-around condition.
QUESTION 6
In which addressing mode is the operand contained explicitly within the
instruction itself?
A. Direct addressing
B. Immediate addressing
C. Indirect addressing
D. Register addressing
Correct Answer: B. Immediate addressing
, Detailed Rationale: In immediate addressing, the field containing the
operand does not specify an address or a register, but rather the actual
data value (operand) to be used.
QUESTION 7
Which CPU register holds the memory address of the next instruction to
be fetched for execution?
A. Accumulator (AC)
B. Instruction Register (IR)
C. Program Counter (PC)
D. Memory Address Register (MAR)
Correct Answer: C. Program Counter (PC)
Detailed Rationale: The Program Counter (PC) is a dedicated register
that keeps track of the execution sequence by storing the address of the
next instruction to be retrieved from memory.
QUESTION 8
Which control unit design stores microinstructions in a control memory
(ROM or RAM) and generates control signals by reading them
sequentially?
A. Hardwired control unit
B. Microprogrammed control unit
C. RISC control unit
D. Pipelined control unit
Correct Answer: B. Microprogrammed control unit
Practice QUESTIONs, Verified Answers & Detailed Explanations
(2026/2027)
QUESTION 1
What is the 8-bit two's complement representation of the decimal
number −45?
A. 11010011
B. 10101100
C. 11010100
D. 00101101
Correct Answer: A. 11010011
Detailed Rationale: First, find the binary representation of +45, which
is 00101101. Next, invert all the bits (one's complement) to get
11010010. Finally, add 1 to the least significant bit: 11010010 + 1 =
11010011.
QUESTION 2
In the IEEE 754 single-precision (32-bit) floating-point format, how
many bits are allocated for the exponent?
A. 8 bits
B. 11 bits
C. 23 bits
D. 32 bits
,Correct Answer: A. 8 bits
Detailed Rationale: The IEEE 754 single-precision format consists of 1
sign bit, 8 exponent bits, and 23 fraction/mantissa bits, totaling 32 bits.
(Double-precision uses 11 bits for the exponent).
QUESTION 3
Which logic gate is universally known as a "universal gate" because any
Boolean function can be implemented using it alone?
A. AND gate
B. OR gate
C. NAND gate
D. XOR gate
Correct Answer: C. NAND gate
Detailed Rationale: Both NAND and NOR gates are universal gates. Any
logical function or gate (AND, OR, NOT) can be constructed using
exclusively NAND gates or exclusively NOR gates.
QUESTION 4
A multiplexer with 16 data inputs requires how many selection lines?
A. 2
B. 3
C. 4
D. 5
Correct Answer: C. 4
,Detailed Rationale: The relationship between data inputs (𝑁) and
selection lines (𝑠) in a multiplexer is 𝑁 = 2𝑠 . For 16 inputs, 2𝑠 = 16,
which means 𝑠 = 4 selection lines are required.
QUESTION 5
Which flip-flop configuration is specifically designed to eliminate the
race-around condition present in standard level-triggered JK flip-flops?
A. SR flip-flop
B. D flip-flop
C. Master-Slave JK flip-flop
D. T flip-flop
Correct Answer: C. Master-Slave JK flip-flop
Detailed Rationale: A Master-Slave flip-flop consists of two cascaded
flip-flops (master and slave) driven by complementary clock pulses. This
prevents the output from changing state while the inputs are still active
during the same clock pulse, avoiding the race-around condition.
QUESTION 6
In which addressing mode is the operand contained explicitly within the
instruction itself?
A. Direct addressing
B. Immediate addressing
C. Indirect addressing
D. Register addressing
Correct Answer: B. Immediate addressing
, Detailed Rationale: In immediate addressing, the field containing the
operand does not specify an address or a register, but rather the actual
data value (operand) to be used.
QUESTION 7
Which CPU register holds the memory address of the next instruction to
be fetched for execution?
A. Accumulator (AC)
B. Instruction Register (IR)
C. Program Counter (PC)
D. Memory Address Register (MAR)
Correct Answer: C. Program Counter (PC)
Detailed Rationale: The Program Counter (PC) is a dedicated register
that keeps track of the execution sequence by storing the address of the
next instruction to be retrieved from memory.
QUESTION 8
Which control unit design stores microinstructions in a control memory
(ROM or RAM) and generates control signals by reading them
sequentially?
A. Hardwired control unit
B. Microprogrammed control unit
C. RISC control unit
D. Pipelined control unit
Correct Answer: B. Microprogrammed control unit
