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Solution Manual for Computer Architecture: A Quantitative Approach, 6th Edition | John L. Hennessy & David A. Patterson

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This Solution Manual for Computer Architecture: A Quantitative Approach, 6th Edition by John L. Hennessy and David A. Patterson is a comprehensive study resource designed to help students master the principles of modern computer architecture. It provides detailed, step-by-step solutions to textbook exercises, reinforcing essential concepts such as instruction set architecture (ISA), processor design, pipelining, memory hierarchy, cache optimization, parallel processing, multicore architectures, performance evaluation, GPU computing, storage systems, cloud computing, and energy-efficient computing. Ideal for students in computer science, computer engineering, and information technology, this resource supports effective coursework, independent learning, and exam preparation while strengthening analytical and problem-solving skills.

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Chapter 1 Solutions
Case Study 1: Chip Fabrication Cost
1.1 a. Yield ¼ 1/(1 + (0.04  2))14 ¼ 0.34
b. It is fabricated in a larger technology, which is an older plant. As plants age,
their process gets tuned, and the defect rate decreases.
1.2 a. Phoenix:
 
Dies per wafer ¼ π  ð45=2Þ2 =2  ðπ  45Þ=sqrtð2  2Þ ¼ 795  70:7 ¼ 724:5 ¼ 724

Yield ¼ 1=ð1 + ð0:04  2ÞÞ14 ¼ 0:340
Profit ¼ 724  0:34  30 ¼ $7384:80

b. Red Dragon:
 
Dies per wafer ¼ π  ð45=2Þ2 =2  ðπ  45Þ=sqrtð2  1:2Þ ¼ 1325  91:25 ¼ 1234

Yield ¼ 1=ð1 + ð0:04  1:2ÞÞ14 ¼ 0:519
Profit ¼ 1234  0:519  15 ¼ $9601:71

c. Phoenix chips: 25,000/724 ¼ 34.5 wafers needed
Red Dragon chips: 50,000/1234 ¼ 40.5 wafers needed
Therefore, the most lucrative split is 40 Red Dragon wafers, 30 Phoenix wafers.
1.3 a. Defect-free single core ¼ Yield ¼ 1/(1 + (0.04  0.25))14 ¼ 0.87
Equation for the probability that N are defect free on a chip:
#combinations  (0.87)N  (1  0.87)8N

# defect-free # combinations Probability
8 1 0.32821167
7 8 0.39234499
6 28 0.20519192
5 56 0.06132172
4 70 0.01145377
3 56 0.00136919
2 28 0.0001023
1 8 4.3673E-06
0 1 8.1573E-08


Yield for Phoenix4: (0.39 + 0.21 + 0.06 + 0.01) ¼ 0.57
Yield for Phoenix2: (0.001 + 0.0001) ¼ 0.0011
Yield for Phoenix1: 0.000004
b. It would be worthwhile to sell Phoenix4. However, the other two have such a
low probability of occurring that it is not worth selling them.

,2 ■ Solutions to Case Studies and Exercises


c. Wafer size
$20 ¼
odd dpw  0:28
Step 1: Determine how many Phoenix4 chips are produced for every
Phoenix8 chip.
There are 57/33 Phoenix4 chips for every Phoenix8 chip ¼ 1.73
$30 + 1:73  $25 ¼ $73:25

Case Study 2: Power Consumption in Computer Systems
1.4 a. Energy: 1/8. Power: Unchanged.
b. Energy: Energynew/Energyold ¼ (Voltage  1/8)2/Voltage2 ¼ 0.156
Power: Powernew/Powerold ¼ 0.156  (Frequency  1/8)/Frequency ¼ 0.00195
c. Energy: Energynew/Energyold ¼ (Voltage  0.5)2/Voltage2 ¼ 0.25
Power: Powernew/Powerold ¼ 0.25  (Frequency  1/8)/Frequency ¼ 0.0313
d. 1 core ¼ 25% of the original power, running for 25% of the time.
0:25  0:25 + ð0:25  0:2Þ  0:75 ¼ 0:0625 + 0:0375 ¼ 0:1

1.5 a. Amdahl’s law: 1/(0.8/4 + 0.2) ¼ 1/(0.2 + 0.2) ¼ 1/0.4 ¼ 2.5
b. 4 cores, each at 1/(2.5) the frequency and voltage
Energy: Energyquad/Energysingle ¼ 4  (Voltage  1/(2.5))2/Voltage2 ¼ 0.64
Power: Powernew/Powerold ¼ 0.64  (Frequency  1/(2.5))/Frequency ¼ 0.256
c. 2 cores + 2 ASICs vs. 4 cores
ð2 + ð0:2  2ÞÞ=4 ¼ ð2:4Þ=4 ¼ 0:6

1.6 a. Workload A speedup: 225,000/13,461 ¼ 16.7
Workload B speedup: 280,000/36,465 ¼ 7.7
1/(0.7/16.7 + 0.3/7.7)
b. General-purpose: 0.70  0.42 + 0.30 ¼ 0.594
GPU: 0.70  0.37 + 0.30 ¼ 0.559
TPU: 0.70  0.80 + 0.30 ¼ 0.886
c. General-purpose: 159 W + (455 W  159 W)  0.594 ¼ 335 W
GPU: 357 W + (991 W  357 W)  0.559 ¼ 711 W
TPU: 290 W + (384 W  290 W)  0.86 ¼ 371 W
d.

Speedup A B C
GPU 2.46 2.76 1.25
TPU 41.0 21.2 0.167
% Time 0.4 0.1 0.5

, Chapter 1 Solutions ■ 3


GPU: 1/(0.4/2.46 + 0.1/2.76 + 0.5/1.25) ¼ 1.67
TPU: 1/(0.4/41 + 0.1/21.2 + 0.5/0.17) ¼ 0.33
e. General-purpose: 14,000/504 ¼ 27.8  28
GPU: 14,000/1838 ¼ 7.62  8
TPU: 14,000/861 ¼ 16.3  17
d. General-purpose: 2200/504 ¼ 4.37  4, 14,000/(4  504) ¼ 6.74  7
GPU: 2200/1838 ¼ 1.2  1, 14,000/(1  1838) ¼ 7.62  8
TPU: 2200/861 ¼ 2.56  2, 14,000/(2  861) ¼ 8.13  9

Exercises
1.7 a. Somewhere between 1.410 and 1.5510, or 28.9  80x
b. 6043 in 2003, 52% growth rate per year for 12 years is 60,500,000 (rounded)
c. 24,129 in 2010, 22% growth rate per year for 15 years is 1,920,000 (rounded)
d. Multiple cores on a chip rather than faster single-core performance
e. 2 ¼ x4, x ¼ 1.032, 3.2% growth
1.8 a. 50%
b. Energy: Energynew/Energyold ¼ (Voltage  1/2)2/Voltage2 ¼ 0.25
1.9 a. 60%
b. 0.4 + 0.6  0.2 ¼ 0.58, which reduces the energy to 58% of the original energy
c. newPower/oldPower ¼ ½Capacitance  (Voltage  0.8)2  (Frequency  0.6)/½
Capacitance  Voltage  Frequency ¼ 0.82  0.6 ¼ 0.256 of the original power.
d. 0.4 + 0.3  2 ¼ 0.46, which reduces the energy to 46% of the original energy
1.10 a. 109/100 ¼ 107
b. 107/107 + 24 ¼ 1
c. [need solution]
1.11 a. 35/10,000  3333 ¼ 11.67 days
b. There are several correct answers. One would be that, with the current system,
one computer fails approximately every 5 min. 5 min is unlikely to be enough
time to isolate the computer, swap it out, and get the computer back on line
again. 10 min, however, is much more likely. In any case, it would greatly
extend the amount of time before 1/3 of the computers have failed at once.
Because the cost of downtime is so huge, being able to extend this is very
valuable.
c. $90,000 ¼ (x + x + x + 2x)/4
$360,000 ¼ 5x
$72,000 ¼ x
4th quarter ¼ $144,000/h

, 4 ■ Solutions to Case Studies and Exercises


12

10

8




Net speedup
6

4

2

0
0 10 20 30 40 50 60 70 80 90 100
Percent vectorization


Figure S.1 Plot of the equation: y 5 100/((100 2 x) + x/10).

1.12 a. See Figure S.1.
b. 2 ¼ 1/((1  x) + x/20)
10/19 ¼ x ¼ 52.6%
c. (0.526/20)/(0.474 + 0.526/20) ¼ 5.3%
d. Extra speedup with 2 units: 1/(0.1 + 0.9/2) ¼ 1.82. 1.82  20  36.4.
Total speedup: 1.95. Extra speedup with 4 units: 1/(0.1 + 0.9/4) ¼ 3.08.
3.08  20  61.5. Total speedup: 1.97
1.13 a. old execution time ¼ 0.5 new + 0.5  10 new ¼ 5.5 new
b. In the original code, the unenhanced part is equal in time to the enhanced part
(sped up by 10), therefore:
(1  x) ¼ x/10
10  10x ¼ x
10 ¼ 11x
10/11 ¼ x ¼ 0.91
1.14 a. 1/(0.8 + 0.20/2) ¼ 1.11
b. 1/(0.7 + 0.20/2 + 0.10  3/2) ¼ 1.05
c. fp ops: 0.1/0.95 ¼ 10.5%, cache: 0.15/0.95 ¼ 15.8%
1.15 a. 1/(0.5 + 0.5/22) ¼ 1.91
b. 1/(0.1 + 0.90/22) ¼ 7.10
c. 41%  22 ¼ 9. A runs on 9 cores. Speedup of A on 9 cores: 1/(0.5 + 0.5/9) ¼
1.8 Overall speedup if 9 cores have 1.8 speedup, others none: 1/(0.6 + 0.4/1.8)
¼ 1.22
d. Calculate values for all processors like in c. Obtain: 1.8, 3, 1.82, 2.5,
respectively.
e. 1/(0.41/1.8 + 0.27/3 + 0.18/1.82 + 0.14/2.5) ¼ 2.12

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