WGU C952 OA EXAM – COMPUTER ARCHITECTURE – SETS
1-5 OBJECTIVE ASSESSMENT – Complete Accurate Test –
Actual Questions – Correct Detailed Answers with Rationales
– Pass Guaranteed - A+ Graded
PRACTICE SET 1: Instruction Set Architecture & Basic Organization
Q1: A team is designing a new embedded processor and wants to keep the hardware
simple while relying on the compiler to optimize code scheduling. Which ISA
characteristic best aligns with this design philosophy?
A. Variable-length instructions with complex addressing modes.
B. Extensive use of microcode to implement multi-cycle operations.
C. Fixed-length instructions and a load-store architecture. [CORRECT]
D. Memory-to-memory operations that bypass the register file.
Correct Answer: C
Rationale: The best answer is C. RISC architectures like MIPS and ARM keep
instructions simple and uniform, which makes the hardware cleaner and lets the
compiler do the heavy lifting. Fixed-length instructions and a load-store design—where
only load and store instructions touch memory—are textbook RISC traits.
Q2: A student is decoding a MIPS instruction and sees the fields: opcode = 0, rs = 8, rt =
9, rd = 10, shamt = 0, funct = 32. Which instruction format is this?
,A. I-type, used for immediate arithmetic and data transfer.
B. J-type, used for unconditional jumps.
C. R-type, used for register-to-register operations. [CORRECT]
D. B-type, used for conditional branches.
Correct Answer: C
Rationale: The best answer is C. When the opcode field is all zeros in MIPS, you're
looking at an R-type instruction. The funct field then tells you exactly which operation to
perform—in this case, 32 corresponds to add. R-type instructions use register fields rs,
rt, and rd, which matches the layout described.
Q3: A program needs to add the constant value 100 to the contents of register $s0.
Which addressing mode does the MIPS instruction addi $s0, $s0, 100 use?
A. Register addressing, because it only operates on registers.
B. Immediate addressing, because the constant is embedded in the instruction.
[CORRECT]
C. Base addressing, because it references memory through a pointer.
D. PC-relative addressing, because the offset is relative to the program counter.
Correct Answer: B
Rationale: The best answer is B. The addi instruction includes a 16-bit immediate value
right in the instruction word. That constant gets sign-extended and fed straight into the
ALU alongside the register value. It's the classic example of immediate addressing in
MIPS.
,Q4: During a function call in MIPS assembly, the processor executes a jal instruction.
Where is the return address automatically stored so the function can return to the
correct location?
A. In register $ra. [CORRECT]
B. On the top of the stack pointed to by $sp.
C. In the program counter without any backup.
D. In a special memory location called the link buffer.
Correct Answer: A
Rationale: The best answer is A. The jal instruction—jump and link—writes the address
of the next instruction (PC + 4) into register $ra (return address). When the function
finishes, it typically uses jr $ra to jump back. That's the standard MIPS calling
convention.
Q5: A compiler developer is choosing between two ISAs for a new system-on-chip. ISA X
uses hundreds of variable-length instructions with complex memory-to-memory
operations. ISA Y uses fifty fixed-length instructions and requires all arithmetic to use
registers. Which statement best describes this tradeoff?
A. ISA X will always produce smaller code and faster execution.
B. ISA Y simplifies hardware decoding but may need more instructions for complex
tasks. [CORRECT]
C. Both ISAs require identical control unit complexity.
D. ISA Y cannot support procedure calls or stack operations.
, Correct Answer: B
Rationale: The best answer is B. ISA X is classic CISC—rich instructions, complex
hardware. ISA Y is classic RISC—simple instructions, clean hardware, but you might
need a few more instructions to accomplish the same high-level task. That's the
fundamental tradeoff C952 students wrestle with.
Q6: A 32-bit little-endian processor stores the 16-bit value 0x1234 at memory address
0x1000. Which byte value sits at address 0x1000?
A. 0x12
B. 0x34 [CORRECT]
C. 0x00
D. 0xFF
Correct Answer: B
Rationale: The best answer is B. In little-endian, the least significant byte goes to the
lowest address. So 0x34—the low byte of 0x1234—lands at 0x1000, and 0x12 lands at
0x1001. It's one of those endianness questions that trips people up if they don't slow
down and think about which byte is which.
Q7: A programmer is writing a MIPS assembly function and needs to know which
registers they are allowed to overwrite without saving them first. According to the
standard calling convention, which registers are caller-saved?
A. $s0 through $s7.
B. $t0 through $t9 and $a0 through $a3. [CORRECT]
1-5 OBJECTIVE ASSESSMENT – Complete Accurate Test –
Actual Questions – Correct Detailed Answers with Rationales
– Pass Guaranteed - A+ Graded
PRACTICE SET 1: Instruction Set Architecture & Basic Organization
Q1: A team is designing a new embedded processor and wants to keep the hardware
simple while relying on the compiler to optimize code scheduling. Which ISA
characteristic best aligns with this design philosophy?
A. Variable-length instructions with complex addressing modes.
B. Extensive use of microcode to implement multi-cycle operations.
C. Fixed-length instructions and a load-store architecture. [CORRECT]
D. Memory-to-memory operations that bypass the register file.
Correct Answer: C
Rationale: The best answer is C. RISC architectures like MIPS and ARM keep
instructions simple and uniform, which makes the hardware cleaner and lets the
compiler do the heavy lifting. Fixed-length instructions and a load-store design—where
only load and store instructions touch memory—are textbook RISC traits.
Q2: A student is decoding a MIPS instruction and sees the fields: opcode = 0, rs = 8, rt =
9, rd = 10, shamt = 0, funct = 32. Which instruction format is this?
,A. I-type, used for immediate arithmetic and data transfer.
B. J-type, used for unconditional jumps.
C. R-type, used for register-to-register operations. [CORRECT]
D. B-type, used for conditional branches.
Correct Answer: C
Rationale: The best answer is C. When the opcode field is all zeros in MIPS, you're
looking at an R-type instruction. The funct field then tells you exactly which operation to
perform—in this case, 32 corresponds to add. R-type instructions use register fields rs,
rt, and rd, which matches the layout described.
Q3: A program needs to add the constant value 100 to the contents of register $s0.
Which addressing mode does the MIPS instruction addi $s0, $s0, 100 use?
A. Register addressing, because it only operates on registers.
B. Immediate addressing, because the constant is embedded in the instruction.
[CORRECT]
C. Base addressing, because it references memory through a pointer.
D. PC-relative addressing, because the offset is relative to the program counter.
Correct Answer: B
Rationale: The best answer is B. The addi instruction includes a 16-bit immediate value
right in the instruction word. That constant gets sign-extended and fed straight into the
ALU alongside the register value. It's the classic example of immediate addressing in
MIPS.
,Q4: During a function call in MIPS assembly, the processor executes a jal instruction.
Where is the return address automatically stored so the function can return to the
correct location?
A. In register $ra. [CORRECT]
B. On the top of the stack pointed to by $sp.
C. In the program counter without any backup.
D. In a special memory location called the link buffer.
Correct Answer: A
Rationale: The best answer is A. The jal instruction—jump and link—writes the address
of the next instruction (PC + 4) into register $ra (return address). When the function
finishes, it typically uses jr $ra to jump back. That's the standard MIPS calling
convention.
Q5: A compiler developer is choosing between two ISAs for a new system-on-chip. ISA X
uses hundreds of variable-length instructions with complex memory-to-memory
operations. ISA Y uses fifty fixed-length instructions and requires all arithmetic to use
registers. Which statement best describes this tradeoff?
A. ISA X will always produce smaller code and faster execution.
B. ISA Y simplifies hardware decoding but may need more instructions for complex
tasks. [CORRECT]
C. Both ISAs require identical control unit complexity.
D. ISA Y cannot support procedure calls or stack operations.
, Correct Answer: B
Rationale: The best answer is B. ISA X is classic CISC—rich instructions, complex
hardware. ISA Y is classic RISC—simple instructions, clean hardware, but you might
need a few more instructions to accomplish the same high-level task. That's the
fundamental tradeoff C952 students wrestle with.
Q6: A 32-bit little-endian processor stores the 16-bit value 0x1234 at memory address
0x1000. Which byte value sits at address 0x1000?
A. 0x12
B. 0x34 [CORRECT]
C. 0x00
D. 0xFF
Correct Answer: B
Rationale: The best answer is B. In little-endian, the least significant byte goes to the
lowest address. So 0x34—the low byte of 0x1234—lands at 0x1000, and 0x12 lands at
0x1001. It's one of those endianness questions that trips people up if they don't slow
down and think about which byte is which.
Q7: A programmer is writing a MIPS assembly function and needs to know which
registers they are allowed to overwrite without saving them first. According to the
standard calling convention, which registers are caller-saved?
A. $s0 through $s7.
B. $t0 through $t9 and $a0 through $a3. [CORRECT]
