WGU D673 ACTUAL EXAM PAPER 2026
QUESTIONS WITH ANSWERS GRADED A+
◍ Stack Architecture.
Answer: no registerIn the 1960s, believing that compilers were not good at
register allocation, some companies eliminated registers and instead
transferred operands onto and off of the stack, similar to what was done in
Hewlett-Packard calculators.
◍ compulsory miss (cold-start miss).
Answer: a cache miss caused by the first access to a block that has never
been in the cacheBoth large block sizes and prefetching may reduce
compulsory misses
◍ B.LT.
Answer: less than
◍ control hazard (branch hazard).
Answer: When the proper instruction cannot execute in the proper pipeline
clock cycle because the instruction that was fetched is not the one that is
needed; that is, the flow of instruction addresses is not what the pipeline
expected.
◍ TLB miss.
Answer: indicates that a page is not in the TLB. Another process then finds
and loads the missing page.
◍ multiprocessor architecture.
Answer: A unified graphics and computing multiprocessor executes vertex,
geometry, and pixel fragment shader programs, and parallel computing
programsadvantages:Increased throughputCost savingIncreased reliability
◍ B.MI.
, Answer: branch on minusN=1
◍ Branch prediction.
Answer: A method of resolving a branch hazard that assumes a given
outcome for the branch and proceeds from that assumption rather than
waiting to ascertain the actual outcome.
◍ RAID 4.
Answer: Block-level striping with dedicated parity. Not often used, replaced
with RAID 5.
◍ IBM 360/91.
Answer: Introduced many new concepts, including dynamic detection of
memory hazards, generalized forwarding, and reservation stations.
Tomasulo's algorithmThe internal organization of the 360/91 shares many
features with the Pentium III and Pentium 4, as well as with several other
microprocessors. One major difference was that there was no branch
prediction in the 360/91 and hence no speculation. Another major difference
was that there was no commit unit, so once the instructions finished
execution, they updated the registers.
◍ Data memory access (MEM).
Answer: the data memory (DM) may be read (for a load instruction) or
written (for a store instruction). For load, the right half is shaded, indicating
read. (For store, the left half would be shaded).
◍ B.VC.
Answer: branch on overflow clearV=0
◍ Tomasulo's Algorithm.
Answer: An algorithm for dynamic scheduling and out-of-order
executionuses dynamic hazard detection, generalized forwarding, and
reservation stations.
◍ IBM 7030.
Answer: AKA StretchProduced with the goal of being 100 times faster than
the previous IBM 704
, ◍ forwarding (bypassing).
Answer: A method of resolving a data hazard by retrieving the missing data
element from internal buffers rather than waiting for it to arrive from
programmer-visible registers or memory
◍ output.
Answer: The results of the operation of any system.
◍ Pipelining.
Answer: Technique that allows the CPU to work on more than one
instruction at a timeFormulatotal process time = [longest task * (total load
-1)] + total load time
◍ wafer.
Answer: A slice from a silicon ingot no more than 0.1 inches thick, used to
create chips.
◍ LDUR.
Answer: load register
◍ ARMv7.
Answer: ARM started as the processor for the Acorn computer, hence its
original name of Acorn RISC Machine. The Berkeley RISC papers
influenced its architecture.
◍ Uniform Memory Access (UMA).
Answer: A multiprocessor in which latency to any word in main memory is
about the same no matter which processor requests the access.
◍ Transistor.
Answer: An on/off switch controlled by an electric signal
◍ supercomputer.
Answer: a particularly powerful mainframe computer.
◍ FADDS, FSUBS.
Answer: Single-precision arithmetic
QUESTIONS WITH ANSWERS GRADED A+
◍ Stack Architecture.
Answer: no registerIn the 1960s, believing that compilers were not good at
register allocation, some companies eliminated registers and instead
transferred operands onto and off of the stack, similar to what was done in
Hewlett-Packard calculators.
◍ compulsory miss (cold-start miss).
Answer: a cache miss caused by the first access to a block that has never
been in the cacheBoth large block sizes and prefetching may reduce
compulsory misses
◍ B.LT.
Answer: less than
◍ control hazard (branch hazard).
Answer: When the proper instruction cannot execute in the proper pipeline
clock cycle because the instruction that was fetched is not the one that is
needed; that is, the flow of instruction addresses is not what the pipeline
expected.
◍ TLB miss.
Answer: indicates that a page is not in the TLB. Another process then finds
and loads the missing page.
◍ multiprocessor architecture.
Answer: A unified graphics and computing multiprocessor executes vertex,
geometry, and pixel fragment shader programs, and parallel computing
programsadvantages:Increased throughputCost savingIncreased reliability
◍ B.MI.
, Answer: branch on minusN=1
◍ Branch prediction.
Answer: A method of resolving a branch hazard that assumes a given
outcome for the branch and proceeds from that assumption rather than
waiting to ascertain the actual outcome.
◍ RAID 4.
Answer: Block-level striping with dedicated parity. Not often used, replaced
with RAID 5.
◍ IBM 360/91.
Answer: Introduced many new concepts, including dynamic detection of
memory hazards, generalized forwarding, and reservation stations.
Tomasulo's algorithmThe internal organization of the 360/91 shares many
features with the Pentium III and Pentium 4, as well as with several other
microprocessors. One major difference was that there was no branch
prediction in the 360/91 and hence no speculation. Another major difference
was that there was no commit unit, so once the instructions finished
execution, they updated the registers.
◍ Data memory access (MEM).
Answer: the data memory (DM) may be read (for a load instruction) or
written (for a store instruction). For load, the right half is shaded, indicating
read. (For store, the left half would be shaded).
◍ B.VC.
Answer: branch on overflow clearV=0
◍ Tomasulo's Algorithm.
Answer: An algorithm for dynamic scheduling and out-of-order
executionuses dynamic hazard detection, generalized forwarding, and
reservation stations.
◍ IBM 7030.
Answer: AKA StretchProduced with the goal of being 100 times faster than
the previous IBM 704
, ◍ forwarding (bypassing).
Answer: A method of resolving a data hazard by retrieving the missing data
element from internal buffers rather than waiting for it to arrive from
programmer-visible registers or memory
◍ output.
Answer: The results of the operation of any system.
◍ Pipelining.
Answer: Technique that allows the CPU to work on more than one
instruction at a timeFormulatotal process time = [longest task * (total load
-1)] + total load time
◍ wafer.
Answer: A slice from a silicon ingot no more than 0.1 inches thick, used to
create chips.
◍ LDUR.
Answer: load register
◍ ARMv7.
Answer: ARM started as the processor for the Acorn computer, hence its
original name of Acorn RISC Machine. The Berkeley RISC papers
influenced its architecture.
◍ Uniform Memory Access (UMA).
Answer: A multiprocessor in which latency to any word in main memory is
about the same no matter which processor requests the access.
◍ Transistor.
Answer: An on/off switch controlled by an electric signal
◍ supercomputer.
Answer: a particularly powerful mainframe computer.
◍ FADDS, FSUBS.
Answer: Single-precision arithmetic
