PLTW Digital Electronics Final Review Set 3 ( Units 1
And 2) With Questions & A+ Solutions
Save
Practice questions for this set
Learn 1 /7 Study using Learn
The rightmost bit of a binary number. This bit has the number's smallest positional
multiplier.
Choose an answer
1 Asynchronous Counter 2 Period
3 Clocked J-K Flip-Flop 4 Least Significant Bit (LSB)
Don't know?
Terms in this set (152)
Asynchronous Counter Type of counter in which each flip-flop output serves
as the clock input signal for the next flip-flop in the
chain
Asynchronous Inputs Flip-flop inputs that can affect the operation of the
flip-flop independent of the synchronous and clock
inputs
,Clock Digital signal in the form of a rectangular pulse train
or a square wave
Clocked D Flip-Flop Type of flip-flop in which the D (data) input is the
synchronous input
Clocked J-K Flip-Flop Type of flip-flop in which the inputs J and K are the
synchronous inputs
D Latch Circuit that contains a NAND gate latch and two
steering NAND gates
Duty Cycle (DC) Fraction of the total period that a digital waveform is
in the HIGH state. DC = th/T (often expressed as a
percentage: %DC = th/Tx100%)
Edge-Sensitive Manner in which a flip-flop is activated by a signal
transition. A flip-flop may be either a positive-or a
negative-edge-triggered flip-flop
Falling Edge The part of a pulse where the logic level is in
transition from a HIGH to a LOW
Flip-Flop A sequential circuit based on a latch whose output
changes when its CLOCK input receives a pulse
Frequency The number of cycles per unit time of a periodic
waveform
Level-Sensitive Enabled by a logic HIGH or LOW level
Period The amount of time required for one complete cycle
of a periodic event or waveform
PRESET Asynchronous input used to set Q=1 immediately
Propagation Delays (tPLH/tPHL) Delay from a time signal is applied to the time when
the output makes its change
, RESET / CLEAR Asynchronous input used to set Q=0 immediately
Rising Edge The part of a pulse where the logic level is in
transition from a LOW to a HIGH
Sequential Logic Digital circuitry in which the output state of the circuit
depends not only on the states of the inputs, but also
on the sequence in which they reached their present
states
Shift Register Digital circuitry that accepts binary data from some
input source and then shifts these data through a
chain of flip-flops one bit at a time
State Machines A sequential circuit that advances through several
defined states
Synchronous Counter Counter in which all of the flip-flops are clocked
simultaneously
Trigger Input signal to a flip-flop or one-shot that causes the
output to change states depending on the conditions
of the control signals
Complex PLD (CPLD) A digital device consisting of several programmable
sections with internal interconnections between the
sections.
Compiler The process used by CPLD design software to
interpret design information (such as a schematic or
text file) and create required programming
information for a CPLD.
Design Entry The process of using software tools to describe the
design requirements of a PLD. Design entry can be
done by entering a schematic or a text file that
describes the required digital function.
And 2) With Questions & A+ Solutions
Save
Practice questions for this set
Learn 1 /7 Study using Learn
The rightmost bit of a binary number. This bit has the number's smallest positional
multiplier.
Choose an answer
1 Asynchronous Counter 2 Period
3 Clocked J-K Flip-Flop 4 Least Significant Bit (LSB)
Don't know?
Terms in this set (152)
Asynchronous Counter Type of counter in which each flip-flop output serves
as the clock input signal for the next flip-flop in the
chain
Asynchronous Inputs Flip-flop inputs that can affect the operation of the
flip-flop independent of the synchronous and clock
inputs
,Clock Digital signal in the form of a rectangular pulse train
or a square wave
Clocked D Flip-Flop Type of flip-flop in which the D (data) input is the
synchronous input
Clocked J-K Flip-Flop Type of flip-flop in which the inputs J and K are the
synchronous inputs
D Latch Circuit that contains a NAND gate latch and two
steering NAND gates
Duty Cycle (DC) Fraction of the total period that a digital waveform is
in the HIGH state. DC = th/T (often expressed as a
percentage: %DC = th/Tx100%)
Edge-Sensitive Manner in which a flip-flop is activated by a signal
transition. A flip-flop may be either a positive-or a
negative-edge-triggered flip-flop
Falling Edge The part of a pulse where the logic level is in
transition from a HIGH to a LOW
Flip-Flop A sequential circuit based on a latch whose output
changes when its CLOCK input receives a pulse
Frequency The number of cycles per unit time of a periodic
waveform
Level-Sensitive Enabled by a logic HIGH or LOW level
Period The amount of time required for one complete cycle
of a periodic event or waveform
PRESET Asynchronous input used to set Q=1 immediately
Propagation Delays (tPLH/tPHL) Delay from a time signal is applied to the time when
the output makes its change
, RESET / CLEAR Asynchronous input used to set Q=0 immediately
Rising Edge The part of a pulse where the logic level is in
transition from a LOW to a HIGH
Sequential Logic Digital circuitry in which the output state of the circuit
depends not only on the states of the inputs, but also
on the sequence in which they reached their present
states
Shift Register Digital circuitry that accepts binary data from some
input source and then shifts these data through a
chain of flip-flops one bit at a time
State Machines A sequential circuit that advances through several
defined states
Synchronous Counter Counter in which all of the flip-flops are clocked
simultaneously
Trigger Input signal to a flip-flop or one-shot that causes the
output to change states depending on the conditions
of the control signals
Complex PLD (CPLD) A digital device consisting of several programmable
sections with internal interconnections between the
sections.
Compiler The process used by CPLD design software to
interpret design information (such as a schematic or
text file) and create required programming
information for a CPLD.
Design Entry The process of using software tools to describe the
design requirements of a PLD. Design entry can be
done by entering a schematic or a text file that
describes the required digital function.
