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WGU C952 COMPUTER ARCHITECTURE - SET 1 -5 EXAM BANK CURRENTLY TESTING COMPLETE EXAM QUESTIONS WITH DETAILED VERIFIED ANSWERS /EXPERT VERIFIED /ALREADY GRADED A+

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WGU C952 COMPUTER ARCHITECTURE - SET 1 -5 EXAM BANK CURRENTLY TESTING COMPLETE EXAM QUESTIONS WITH DETAILED VERIFIED ANSWERS /EXPERT VERIFIED /ALREADY GRADED A+

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WGU C952 COMPUTER ARCHITECTURE - SET 1 -5 EXAM BANK CURRENTLY
TESTING COMPLETE EXAM QUESTIONS WITH DETAILED VERIFIED ANSWERS
/EXPERT VERIFIED /ALREADY GRADED A+


Question 1
Which of the following best defines "Response Time" (also known as Execution Time) in the
context of computer performance?
A) The total number of instructions executed per second.
B) The time between the start and the completion of a specific task.
C) The amount of work done by a computer in a given period of time.
D) The frequency of the internal processor clock.
E) The time it takes for a signal to travel across the bus.

Correct Answer: B) The time between the start and the completion of a specific task.
Rationale: Response time is the most direct measure of performance from a user's
perspective. It includes everything involved in the task: CPU time, disk access, memory
access, I/O activities, and operating system overhead. It is distinct from throughput, which
measures how many tasks a system can handle in a set window (Option C), and clock
frequency (Option D), which is just one component that influences response time.

Question 2
If a computer's performance is increased by a factor of 10 for a specific task, how is the
"Performance" mathematically related to the "Execution Time"?
A) Performance = 1 / Execution Time
B) Performance = Execution Time²
C) Performance = Execution Time + Clock Rate
D) Performance = Instruction Count / CPI
E) Performance = Execution Time / 10

Correct Answer: A) Performance = 1 / Execution Time
Rationale: In computer architecture, performance and execution time are reciprocals. To
maximize performance, we must minimize execution time. Therefore, if Computer A is
"faster" than Computer B, the execution time of A must be lower than B. The ratio of
performance is calculated as Performance_A / Performance_B = Execution_Time_B /
Execution_Time_A.

, 2



Question 3
Amdahl's Law is primarily used to:
A) Calculate the total power consumption of a multi-core processor.
B) Determine the maximum number of transistors that can fit on a die.
C) Predict the theoretical speedup of a task when only a portion of the task is improved.
D) Measure the cache hit rate in a direct-mapped configuration.
E) Solve for the number of stages required in a deep pipeline.

Correct Answer: C) Predict the theoretical speedup of a task when only a portion of the task
is improved.
Rationale: Amdahl’s Law provides a reality check for performance enhancement. It states
that the improvement gained by optimizing one part of a system is limited by the fraction
of time that the improved part is actually used. Even if you make a specific component 100
times faster, if that component is only used for 1% of the total execution time, the overall
system speedup will be negligible (less than 1.01x).

Question 4
In the MIPS architecture, which register is hardwired to the value zero and cannot be
overwritten?
A) $s0
B) $t0
C) $v0
D) $zero
E) $ra

Correct Answer: D) $zero
Rationale: Register $0 (referred to as $zero) in MIPS is permanently set to 0. This is a
design choice that simplifies the instruction set. It allows for common operations to be
performed using standard instructions. For example, moving a value from $t1 to $t2 can be
done using 'add $t2, $t1, $zero'. It also provides a constant source for comparisons (beq
$t1, $zero, label).

, 3



Question 5
Which of the following MIPS instruction types is used for operations that require two source
registers and one destination register, such as "add"?
A) I-type
B) J-type
C) R-type
D) S-type
E) M-type

Correct Answer: C) R-type
Rationale: R-type (Register-type) instructions are used for computational operations where
all operands reside in registers. The 32-bit R-type instruction is divided into fields: opcode
(6 bits), rs (5 bits), rt (5 bits), rd (5 bits), shamt (5 bits), and funct (6 bits). 'rs' and 'rt' are
the source registers, while 'rd' is the destination register.

Question 6
What is the primary difference between a "Word" and a "Byte" in the MIPS architecture?
A) A byte is 32 bits; a word is 8 bits.
B) A byte is 8 bits; a word is 32 bits.
C) A byte is 16 bits; a word is 64 bits.
D) There is no difference; they are used interchangeably.
E) A word is used for floating point; a byte is used for integers.

Correct Answer: B) A byte is 8 bits; a word is 32 bits.
Rationale: Standard MIPS architecture uses 32-bit words. Since each byte consists of 8 bits,
a single MIPS word is composed of 4 bytes. This distinction is crucial for memory
addressing; because MIPS is byte-addressed, word addresses must be multiples of 4
(alignment restriction).

Question 7
The MIPS instruction "lw

𝑡0,12(

, 4



s1)" performs which of the following actions?
A) Stores the value in $t0 into the memory address $s1 + 12.
B) Loads the value from memory address $s1 + 12 into $t0.
C) Adds 12 to $s1 and stores the result in $t0.
D) Loads the value 12 into register $t0.
E) Multiplies $s1 by 12 and loads it into $t0.

Correct Answer: B) Loads the value from memory address $s1 + 12 into

𝑡0.∗∗ 𝑅𝑎𝑡𝑖𝑜𝑛𝑎𝑙𝑒:∗∗ 𝑇ℎ𝑒 ′ 𝑙𝑤 ′ (𝑙𝑜𝑎𝑑𝑤𝑜𝑟𝑑)𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑖𝑠𝑎𝑛𝐼
− 𝑡𝑦𝑝𝑒𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑢𝑠𝑒𝑑𝑓𝑜𝑟𝑑𝑎𝑡𝑎𝑡𝑟𝑎𝑛𝑠𝑓𝑒𝑟𝑓𝑟𝑜𝑚𝑚𝑒𝑚𝑜𝑟𝑦𝑡𝑜𝑎𝑟𝑒𝑔𝑖𝑠𝑡𝑒𝑟. 𝑇ℎ𝑒𝑚𝑒𝑚𝑜𝑟𝑦𝑎𝑑𝑑𝑟𝑒𝑠𝑠𝑖𝑠𝑐𝑎𝑙𝑐𝑢𝑙𝑎𝑡𝑒𝑑

s1). This is called base-offset or displacement addressing.

Question 8
Which MIPS instruction field determines the specific operation for R-type instructions, given
that their opcode is always 0?
A) rs
B) rt
C) rd
D) funct
E) shamt

Correct Answer: D) funct
Rationale: In MIPS, all R-type instructions share the opcode 000000. To distinguish between
different R-type operations like 'add', 'sub', or 'and', the processor looks at the 'funct'
(function) field, which occupies the last 6 bits of the instruction. This allows for a larger
variety of register-to-register operations than the opcode field alone would support.

Question 9
What is the range of a 16-bit immediate value in a MIPS I-type instruction when treated as a
two's complement signed integer?
A) 0 to 65,535
B) -32,768 to 32,767

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