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Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs
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3

August 2024

2024/2025

A+
One of the emerging architectures/technologies for future chips is wafer-level three-dimensional (3D) integration [1,2], i.e., fabrication of functional components (e.g., logic and memory) on separate wafers, followed by wafer aligning, bonding, thinning and vertical inter-wafer interconnection [3]. The 3D integration offers high interconnect performance by reducing delays of global interconnects [2] and high functionality with heterogeneous integration of materials, devices, and signals...
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