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ECE 260: Digital Logic Design Question & Answers
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ECE 260: Digital Logic Design Question & Answers 
(A + B)' = A'B' - ANSWER: DeMorgan OR to AND 
(AB)' = A' + B' - ANSWER: DeMorgan AND to OR 
0 - ANSWER: ALU M = x for arithmetic 
0 to 1 - ANSWER: +ve or rising edge - change occurs when CLK 
1 - ANSWER: ALU M = x for logic 
1 to 0 - ANSWER: -ve or falling edge - change occurs when CLK 
10 - (sum % 10) - ANSWER: POSTNET checksum formula 
10 ns - ANSWER: Delay time ~ 
1024 - ANSWER: 1K in bits 
2^20 - ANSWER: 1M in bits 
2^m = n + 1 - ANSWER...
Digital Signal Processing Package, Questions & Answers
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DIGITAL LOGIC DESIGN QUESTIONS & ANSWERS
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DIGITAL LOGIC DESIGN QUESTIONS & ANSWERS 
0 and 1 - CORRECT ANSWER- as subtraction goes, the only time the circuit will use borrow is 
when the subtrahend is ____ while the minuend is ____ 
1. Arithmetic and Logical Functions 
2. Data Transmission 
3. Code Converters - CORRECT ANSWER- CLC three classifications 
7-segment display - CORRECT ANSWER- convenient way of displaying information or digital 
data in form of numbers or letters 
7-segment display - CORRECT ANSWER- typically consists of seve...
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Digital Logic Design Questions & Answers
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Digital Logic Design Questions & Answers 
- LAN - CORRECT ANSWER- - network that connects computers & devices in a small area. 
- Advantages - Low Cost, Easy configuration, Speed. 
- Disadvantages - Low safety and security, not able to handle large amounts of computers. 
1. What is SMP? List advantages. - CORRECT ANSWER- A computing design where two or 
more processors are attached to a single memory and operating system. 
- Advantages: greater performance, scaling (range of products & prices), ...
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Digital Logic Design Questions & Answers
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Digital Logic Design Questions & Answers 
A logic designer needs an INVERTER, and all that is available is one XOR gate from a 74HC86 
chip. Does he need another chip? - CORRECT ANSWER- 3. No; the available XOR gate can 
be used as an INVERTER by connecting one of its inputs to a constant HIGH (see Example 4- 
16). 
Change each AND gate in Figure 4-1(a) to a NAND gate. Determine the new expression for x 
and simplify it. - CORRECT ANSWER- x=A+B+C^lineAll 
Define hierarchical design. - CORRECT AN...
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Digital Logic Design Unit 1 Questions & Answers
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Digital Logic Design Unit 1 Questions & Answers 
(A+B)(A+C) - CORRECT ANSWER- A+BC 
A+~AB - CORRECT ANSWER- A+B 
A+AB= - CORRECT ANSWER- A 
Advantage of circuits to represent boolean functions: - CORRECT ANSWER- A circuit is an 
interconnection of components. Different circuits can represent the same function. 
Advantage: Circuit may represent an actual physical implementation of a Boolean function and 
that a circuit drawn graphically can enable quick and easy comprehension of a function by 
hu...
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Exam 1- Digital Logic Design Questions & Answers
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Exam 1- Digital Logic Design Questions & Answers 
adjacency - CORRECT ANSWER- ab + ab' = a 
a(b + b') 
a * 1 
(a + b)(a+b') = a 
AND - CORRECT ANSWER- gate? a * b 
associative - CORRECT ANSWER- a + (b + c) = (a + b) + c 
a(bc) + (ab)c 
canonical POS - CORRECT ANSWER- a POS expression where each sum term is a maxterm 
canonical SOP - CORRECT ANSWER- an SOP where all product terms are minterms - - each 
product term contains all variables 
EX. f(x,y,z) = x'yz' + xy'z' + xyz' +xyz 
commutat...
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Digital Logic Design Questions & Answers
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Digital Logic Design Questions & Answers 
2 Main types of Transistors - CORRECT ANSWER- 1. FET 2. BJT 
Amplitude - CORRECT ANSWER- Height from Baseline 
Analog - CORRECT ANSWER- Continuous Values (temperature, height, light, voice) 
bit - CORRECT ANSWER- Binary Digit 
BJT - CORRECT ANSWER- Bipolar Junction Transistor Used in TTL and are large 
Characteristics of a Pulse - CORRECT ANSWER- 1. Rise time 2. Fall time. 3. pulse width 4. 
amplitude 
Clock - CORRECT ANSWER- Basic Timing Signal in digit...
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Digital Logic Design Questions & Answers
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Digital Logic Design Questions & Answers 
0 - CORRECT ANSWER- The identity element for OR 
0 - CORRECT ANSWER- The null element for AND 
3 - CORRECT ANSWER- A group of 4 ones in a 5-variable k-map is simplified to a product 
term of... variables 
3 - CORRECT ANSWER- Maximum Delay in F(x,y,z)= (x+y)(zy)+x, if it is implemented as it 
is 

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Digital Logic Design Final Questions & Answers
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Digital Logic Design Final Questions & Answers 
A combinational circuit is a zeroth-stage pipeline - CORRECT ANSWER- True 
A combinational device is a circuit element that has: (mark all correct): - CORRECT 
ANSWER- one or more digital outputs 
one or more digital inputs 
a functional specification 
A disadvantage of a programmable control system is that we cannot reconfigure it to compute 
new functions - CORRECT ANSWER- False 
A Don't Care is just a(n) [first] (and) [second] that the [third] ...
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