ECE 260: Digital Logic Design Question & Answers

ECE 260: Digital Logic Design Question & Answers (A + B)' = A'B' - ANSWER: DeMorgan OR to AND (AB)' = A' + B' - ANSWER: DeMorgan AND to OR 0 - ANSWER: ALU M = x for arithmetic 0 to 1 - ANSWER: +ve or rising edge - change occurs when CLK 1 - ANSWER: ALU M = x for logic 1 to 0 - ANSWER: -ve or falling edge - change occurs when CLK 10 - (sum % 10) - ANSWER: POSTNET checksum formula 10 ns - ANSWER: Delay time ~ 1024 - ANSWER: 1K in bits 2^20 - ANSWER: 1M in bits 2^m = n + 1 - ANSWER: Redundancy formula 4096 - ANSWER: 4K in bits 74210 - ANSWER: POSTNET weighting A and B different - ANSWER: XOR description A and B same - ANSWER: XNOR description Add 3 to binary - ANSWER: XS3 Answer is a different sign than addends - ANSWER: Conditions for overflow Application Specific IC - ANSWER: ASIC Arithmetic Logic Unit (Acronym) - ANSWER: ALU bit - ANSWER: 1 unit byte - ANSWER: 8 units C makes even parity - ANSWER: XOR and parity