Topic V04
Data Transfer Between
Memory and Registers
1
, Example of a lw execution
RISC-V assembly lw
base address
t0, 8(s1) # t0 ← A[2]
t0
Data Bus
t1
t2
registers
Memory
s0 Cells
Memory
s1 + Controller
s2
s3 8
qanaopaawy
gg
Processor
Read Address Bus
Control
Unit usedtoteamemory
wanttodoBus
Control
2
Data Transfer Between
Memory and Registers
1
, Example of a lw execution
RISC-V assembly lw
base address
t0, 8(s1) # t0 ← A[2]
t0
Data Bus
t1
t2
registers
Memory
s0 Cells
Memory
s1 + Controller
s2
s3 8
qanaopaawy
gg
Processor
Read Address Bus
Control
Unit usedtoteamemory
wanttodoBus
Control
2
