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Computer
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Architecture - Exam 2 Questions With Correct
/ // // // // // //
Answers
//
*Main //memory* //is //made //of //what //type //of //RAM? //- //CORRECT //ANSWERS(S)✔✔DRAM
How /
/do /
/DRAM /
/cells /
/store /
/data? //- /
/CORRECT /
/ANSWERS(S)✔✔As /
/charge /
/on /
/capacitors //-- /
/the /
/presence /
/of //
a/
/charge /
/in /
/an /
/upper /
/range /
/is /
/interpreted /
/as //a //1, //and //the //presence //of //a //charge //in //a //lower //range //is //interpreted //as //a //0
,Which //type //of //RAM //requires //periodic //refresh? //- //CORRECT //ANSWERS(S)✔✔DRAM
Which //type //of //RAM //has //a //higher //access //time? //- //CORRECT //ANSWERS(S)✔✔DRAM
A //*cache* //is //made //of //what //type //of //RAM? //- //CORRECT //ANSWERS(S)✔✔SRAM
How /
/do /
/SRAM /
/cells //store //data? //- //CORRECT //ANSWERS(S)✔✔Through //traditional //flip //flop //logic //gates
True /
/or /
/false: /
/SRAM /
/will //hold //its //data //as //long //as //power //is //supplied //to //it //- //CORRECT //ANSWERS(S)✔✔True
Which //has //a //greater //cost //per //bit: //SRAM //or //DRAM? //- //CORRECT //ANSWERS(S)✔✔SRAM
True /
/or //false: //SRAM //cells //must //be //refreshed //periodically //- //CORRECT //ANSWERS(S)✔✔False
Looking //at //the //DRAM //cell //diagram:
1. //How //do //reads //work?
2. /
/How /
/do /
/writes /
/work? //- //CORRECT //ANSWERS(S)✔✔1. //When //the //cell //is //being //read //from, //the //address //line
,//is /
/activated, /
/closing /
/the /
/transistor /
/and /
/allowing /
/current //to //flow. //The //charge //stored //on //the //capacitor //is //fed //out //onto //the //bit //line, //where
//it //is //read //by //a //sense //amplifier.
2. /
/When /
/the /
/cell /
/is /
/being /
/written /
/to, /
/the /
/address /
/line /
/is /
/activated, /
/closing /
/the /
/transistor /
/and /
/allowing /
/current /
/to /
/flow. //
A/
/voltage /
/signal /
/will /
/be /
/applied /
, /to /
/the /
/bit /
/line: //
a/
/high /
/voltage /
/signal /
/is /
/1, //
a/
/low /
/voltage //signal //is //0. //This //voltage //signal //is //transferred //into //and //stored //in //the //capacitor.
Looking //at //the //SRAM //cell //diagram:
1. //How //do //reads //work?
2. //How //do //writes //work? //- //CORRECT //ANSWERS(S)✔✔Four //transistors //are //cross-
connected /
/in /
/an /
/arrangement /
/that /
/produces //
a/
/stable /
/logic /
/state. /
/When //an //address //is //sent //on //the //address //line, //two //extra //transistors //open //up //to //allow //a
//read //or //write //operation.
1. //The //bit //value //is //read //from //the //bit //line.
Computer
/ /
Architecture - Exam 2 Questions With Correct
/ // // // // // //
Answers
//
*Main //memory* //is //made //of //what //type //of //RAM? //- //CORRECT //ANSWERS(S)✔✔DRAM
How /
/do /
/DRAM /
/cells /
/store /
/data? //- /
/CORRECT /
/ANSWERS(S)✔✔As /
/charge /
/on /
/capacitors //-- /
/the /
/presence /
/of //
a/
/charge /
/in /
/an /
/upper /
/range /
/is /
/interpreted /
/as //a //1, //and //the //presence //of //a //charge //in //a //lower //range //is //interpreted //as //a //0
,Which //type //of //RAM //requires //periodic //refresh? //- //CORRECT //ANSWERS(S)✔✔DRAM
Which //type //of //RAM //has //a //higher //access //time? //- //CORRECT //ANSWERS(S)✔✔DRAM
A //*cache* //is //made //of //what //type //of //RAM? //- //CORRECT //ANSWERS(S)✔✔SRAM
How /
/do /
/SRAM /
/cells //store //data? //- //CORRECT //ANSWERS(S)✔✔Through //traditional //flip //flop //logic //gates
True /
/or /
/false: /
/SRAM /
/will //hold //its //data //as //long //as //power //is //supplied //to //it //- //CORRECT //ANSWERS(S)✔✔True
Which //has //a //greater //cost //per //bit: //SRAM //or //DRAM? //- //CORRECT //ANSWERS(S)✔✔SRAM
True /
/or //false: //SRAM //cells //must //be //refreshed //periodically //- //CORRECT //ANSWERS(S)✔✔False
Looking //at //the //DRAM //cell //diagram:
1. //How //do //reads //work?
2. /
/How /
/do /
/writes /
/work? //- //CORRECT //ANSWERS(S)✔✔1. //When //the //cell //is //being //read //from, //the //address //line
,//is /
/activated, /
/closing /
/the /
/transistor /
/and /
/allowing /
/current //to //flow. //The //charge //stored //on //the //capacitor //is //fed //out //onto //the //bit //line, //where
//it //is //read //by //a //sense //amplifier.
2. /
/When /
/the /
/cell /
/is /
/being /
/written /
/to, /
/the /
/address /
/line /
/is /
/activated, /
/closing /
/the /
/transistor /
/and /
/allowing /
/current /
/to /
/flow. //
A/
/voltage /
/signal /
/will /
/be /
/applied /
, /to /
/the /
/bit /
/line: //
a/
/high /
/voltage /
/signal /
/is /
/1, //
a/
/low /
/voltage //signal //is //0. //This //voltage //signal //is //transferred //into //and //stored //in //the //capacitor.
Looking //at //the //SRAM //cell //diagram:
1. //How //do //reads //work?
2. //How //do //writes //work? //- //CORRECT //ANSWERS(S)✔✔Four //transistors //are //cross-
connected /
/in /
/an /
/arrangement /
/that /
/produces //
a/
/stable /
/logic /
/state. /
/When //an //address //is //sent //on //the //address //line, //two //extra //transistors //open //up //to //allow //a
//read //or //write //operation.
1. //The //bit //value //is //read //from //the //bit //line.
