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ECEN 350 Exam 1 Studying questions with complete solutions

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ECEN 350 Exam 1 Studying questions with complete solutions

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ECEN 350 Exam 1 Studying questions
with complete solutions

Moore's Law

The number of transistors per square inch on integrated circuits doubles every year.




Computer processor cores directly execute the high-level code you write

False




A higher frequency processor will always have higher performance than a lower frequency
processor.

False




An easy way to reduce the energy consumption needed to compute a given job is to decrease
its ___________.

Frequency, clock, or GHz




Decreasing response time should have no impact on throughput.

False

,The processor directly executes the code you write in C, Java, C++, etc.

False




There is a one-to-one matching between lines of C and lines of an assembly language.

False




There is a one-to-one matching between lines of an assembly language and lines of its machine
language.

True




The compiler will always produce better performing assembly than a human can.

False




Given the following mix of instruction classes and CPIs, calculate the weighted average CPI for
the program on a given CPU.

Class A:

percentage: 30%

CPI: 2

Class B:

percentage: 20%

CPI: 3

Class C:

percentage: 50%

, CPI: 1

1.7




Given two different computers A and B of the same ISA, running the same application binary,
what is the speedup of A over B?

A: CPI = 1.5, Frequency = 2GHz

B: CPI = 1, Frequency = 1.5GHz

CPUtimea = I*1.5/2GHz

CPUtimeb = I*1/1.5GHz

Speedup a/b = 2G/1.5*1.5G = .8889




Imagine you have converted a single threaded program to multi-threaded so it can execute on a
multi-core processor. You can support as many threads as there are processors but there
remains a 5% overhead which cannot be parallelized. What is the maximum speedup you can
expect with an infinite core machine?

20x




___________ is a good measure of the time a processor spent on a given job.

CPU time




ARMv8 and many other RISC ISAs are considered to be a "Load/Store Architecture" because
many computational instructions operate directly on the memory.

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