EEL 4713C
Digital Computer Architecture
4.0 Credits
Final Exam Review (Qns & Ans)
2025
©2025
, Multiple Choice Questions (10 Questions)
1. Question:
In a pipelined processor, which hazard arises when an instruction
depends on the result of a previous instruction that has not yet
completed its execution?
a. Structural hazard
b. Data hazard
c. Control hazard
d. Resource hazard
ANS:
b. Data hazard
Rationale:
Data hazards occur when instructions exhibit dependencies on
the results of prior instructions. This may force pipeline stalls unless
resolved by techniques such as forwarding or register renaming.
2. Question:
Which design architecture allows a processor to issue multiple
instructions in a single clock cycle by having more than one
execution unit?
a. Single‑cycle processor
b. Superscalar architecture
c. Vector processor
d. RISC architecture
ANS:
b. Superscalar architecture
Rationale:
Superscalar architectures feature multiple execution units
capable of dispatching and completing more than one instruction
per clock cycle, increasing instruction throughput.
3. Question:
©2025
, What technique is employed in modern processors to reduce the
penalty of branch mispredictions by guessing the likely branch
path?
a. Static scheduling
b. Loop unrolling
c. Branch prediction
d. Out‑of‑order execution
ANS:
c. Branch prediction
Rationale:
Branch prediction guesses the direction of a branch before its
condition is evaluated. Advanced predictors (e.g., two-level
adaptive predictors) are now common to improve performance.
4. Question:
In a multilevel cache hierarchy, the L1 cache is typically
characterized by which of the following?
a. High latency and large capacity
b. Low latency and small capacity
c. High capacity and low clock speed
d. Directly connected to main memory
ANS:
b. Low latency and small capacity
Rationale:
The L1 cache is very fast with low latency to meet the processor’s
speed demands. However, it is small in size compared to L2 or L3
caches, which trade speed for capacity.
5. Question:
Out‑of‑order execution in a processor primarily improves
performance by:
a. Reducing the clock cycle time
b. Eliminating branch instructions
©2025
Digital Computer Architecture
4.0 Credits
Final Exam Review (Qns & Ans)
2025
©2025
, Multiple Choice Questions (10 Questions)
1. Question:
In a pipelined processor, which hazard arises when an instruction
depends on the result of a previous instruction that has not yet
completed its execution?
a. Structural hazard
b. Data hazard
c. Control hazard
d. Resource hazard
ANS:
b. Data hazard
Rationale:
Data hazards occur when instructions exhibit dependencies on
the results of prior instructions. This may force pipeline stalls unless
resolved by techniques such as forwarding or register renaming.
2. Question:
Which design architecture allows a processor to issue multiple
instructions in a single clock cycle by having more than one
execution unit?
a. Single‑cycle processor
b. Superscalar architecture
c. Vector processor
d. RISC architecture
ANS:
b. Superscalar architecture
Rationale:
Superscalar architectures feature multiple execution units
capable of dispatching and completing more than one instruction
per clock cycle, increasing instruction throughput.
3. Question:
©2025
, What technique is employed in modern processors to reduce the
penalty of branch mispredictions by guessing the likely branch
path?
a. Static scheduling
b. Loop unrolling
c. Branch prediction
d. Out‑of‑order execution
ANS:
c. Branch prediction
Rationale:
Branch prediction guesses the direction of a branch before its
condition is evaluated. Advanced predictors (e.g., two-level
adaptive predictors) are now common to improve performance.
4. Question:
In a multilevel cache hierarchy, the L1 cache is typically
characterized by which of the following?
a. High latency and large capacity
b. Low latency and small capacity
c. High capacity and low clock speed
d. Directly connected to main memory
ANS:
b. Low latency and small capacity
Rationale:
The L1 cache is very fast with low latency to meet the processor’s
speed demands. However, it is small in size compared to L2 or L3
caches, which trade speed for capacity.
5. Question:
Out‑of‑order execution in a processor primarily improves
performance by:
a. Reducing the clock cycle time
b. Eliminating branch instructions
©2025
