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EEL 3701C Digital Logic & Computer Systems Final Exam Review 2025 (Qns & Ans).

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EEL 3701C Digital Logic & Computer Systems Final Exam Review 2025 (Qns & Ans).EEL 3701C Digital Logic & Computer Systems Final Exam Review 2025 (Qns & Ans).EEL 3701C Digital Logic & Computer Systems Final Exam Review 2025 (Qns & Ans).

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Uploaded on
May 6, 2025
Number of pages
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Written in
2024/2025
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Exam (elaborations)
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EEL 3701C

Digital Logic & Computer Systems

4.0 Credits

Final Exam Review (Qns & Ans)

2025




©2025

, Multiple Choice Questions

1. Question:
Which Boolean algebra principle states that the validity of any algebraic
expression remains unchanged if AND and OR operators, as well as 0 and
1, are interchanged?
a) Shannon's Expansion
b) Duality Principle
c) De Morgan's Law
d) Consensus Theorem

ANS:
b) Duality Principle

Rationale:
The duality principle affirms that each true Boolean identity remains
valid if all AND operators are replaced by OR operators, all OR operators
by AND operators, and 0’s by 1’s (and vice versa).

2. Question:
Which of the following circuits converts a one‑hot input (only one input
is high) into its corresponding binary code?
a) Decoder
b) Encoder
c) Multiplexer
d) Demultiplexer

ANS:
b) Encoder

Rationale:
An encoder accepts one–hot inputs and produces the binary
representation of the active input, making it essential in data
compression and digital control applications.


©2025

, 3. Question:
A digital circuit element that updates its output only on a clock edge is
known as a:
a) Latch
b) D flip‑flop
c) SR flip‑flop
d) Transparent latch

ANS:
b) D flip‑flop

Rationale:
The D flip‑flop, being edge‑triggered, samples the D input on the active
clock edge (rising or falling) and is fundamental for synchronous designs.

4. Question:
Which hardware description language is most widely used for designing
FPGAs and ASICs?
a) C++
b) Verilog
c) Python
d) Java

ANS:
b) Verilog

Rationale:
Verilog is a dominant language in the digital design community for
modeling, simulating, and synthesizing digital circuits in both FPGA and
ASIC projects.

5. Question:
The parameter that represents the time required for a signal change at
the input of a digital circuit to produce a corresponding change at the
output is known as:
©2025

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