Computer Architecture Test Final
Question and answers verified to pass
OP code - correct answer ✔The portion (bit field) of a machine language
instruction that specifies the operation to be done by the CPU.
Control Transfer Instruction - correct answer ✔A type of instruction that
modifies the machine's program counter (other than by simply incrementing
it).
Indexed Addressing - correct answer ✔A way of specifying the location of an
operand in memory by adding a constant embedded in the instruction to the
contents of a "pointer" register inside the CPU.
Zero-Operand Instruction - correct answer ✔These would be characteristic of
a stack-based instruction set.
Accumulater Machine - correct answer ✔This type of architecture typically
has instructions that
explicitly specify only one operand.
Load-Store Architecture - correct answer ✔A feature of some computer
architectures where "operate"
instructions do not have memory operands; their operands are found in CPU
registers.
Complex Instruction Set Computer (CISC) - correct answer ✔Machines
belonging to this architectural class try to "bridge the semantic gap" by having
machine language instructions that approximate the functionality of high-level
language statements.
,Datapath - correct answer ✔This part of a CPU includes the registers that
store operands as well as the circuitry that performs computations.
Carry Lookahead Adder - correct answer ✔This type of addition circuit
develops all carries in logic, directly from the inputs, rather than waiting for
them to propagate from less significant bit positions.
Wallace Tree - correct answer ✔A structure comprised of multiple levels of
carry save adders, which can be used to efficiently implement multiplication.
Excess (biased) Notation - correct answer ✔This type of notation stores
signed numbers as though they
were unsigned; it is used to represent exponents in some floating-point
formats.
Significand (fraction) - correct answer ✔In IEEE-754 floating-point numbers,
a normalized mantissa with the leading 1 omitted is called this.
Positive Infinity - correct answer ✔This is the result when the operation
1.0/0.0 is performed on a system with IEEE-754 floating-point arithmetic.
Instruction Register (IR) - correct answer ✔This holds the currently executing
machine language
instruction so its bits can be decoded and interpreted by the control unit.
Microroutine - correct answer ✔A sequence of microinstructions that fetches
or executes a machine language instruction, initiates exception processing, or
carries out some other basic machine-level task.
,Horizontal Microprogramming - correct answer ✔A technique used in
microprogrammed control unit
design in which mutually-exclusive control signals are not encoded into bit
fields, thus eliminating the need for decoding microinstructions.
Flow-Through Time - correct answer ✔The time required for the first result in
a series of computations to emerge from a pipeline.
Pipeline Register - correct answer ✔This is used to separate one stage of a
pipeline from the next.
Pipeline Throughput - correct answer ✔Over time, this tells the mean
number of operations completed per clock cycle.
Branch Penalty - correct answer ✔The clock cycles that are wasted by an
instruction-pipelined processor due to executing a control transfer instruction.
Static Branch Prediction - correct answer ✔A technique used in pipelined
CPUs where the compiler supplies a hint as to whether or not a given
conditional branch is likely to succeed.
Delay Slot Instruction(s) - correct answer ✔The instruction(s) immediately
following a conditional
control transfer instruction in some pipelined processors, which are executed
whether or not the control transfer occurs.
Delayed Load - correct answer ✔A technique used in pipelined CPUs where
the instruction immediately following another instruction that reads a memory
operand cannot use the updated value
of the operand.
, Read After Write (RAW) Hazard - correct answer ✔The most common data
hazard in pipelined
processors; also known as a true data dependence.
Write After Write (WAW) Hazard - correct answer ✔Also known as an output
dependence, this hazard
can occur in a processor that utilizes out-of-order execution.
Scoreboard - correct answer ✔A centralized resource scheduling
mechanism for internally concurrent processors; it was first used in the CDC
6600 supercomputer.
Reservation Stations - correct answer ✔These are used by a Tomasulo
scheduler to hold operands for functional units.
Overlapping Register Windows - correct answer ✔A feature of some
instruction set architectures (e.g. SPARC) that attempts to optimize
application performance by avoiding the use of procedure parameters stored
on stack frames
Superpipelined - correct answer ✔This type of processor architecture
maximizes temporal parallelism by using a very deep pipeline with very fast
stages.
Predication - correct answer ✔The IA-64 architecture uses this approach
instead of branch prediction to minimize the disruption caused by conditional
control transfers.
Question and answers verified to pass
OP code - correct answer ✔The portion (bit field) of a machine language
instruction that specifies the operation to be done by the CPU.
Control Transfer Instruction - correct answer ✔A type of instruction that
modifies the machine's program counter (other than by simply incrementing
it).
Indexed Addressing - correct answer ✔A way of specifying the location of an
operand in memory by adding a constant embedded in the instruction to the
contents of a "pointer" register inside the CPU.
Zero-Operand Instruction - correct answer ✔These would be characteristic of
a stack-based instruction set.
Accumulater Machine - correct answer ✔This type of architecture typically
has instructions that
explicitly specify only one operand.
Load-Store Architecture - correct answer ✔A feature of some computer
architectures where "operate"
instructions do not have memory operands; their operands are found in CPU
registers.
Complex Instruction Set Computer (CISC) - correct answer ✔Machines
belonging to this architectural class try to "bridge the semantic gap" by having
machine language instructions that approximate the functionality of high-level
language statements.
,Datapath - correct answer ✔This part of a CPU includes the registers that
store operands as well as the circuitry that performs computations.
Carry Lookahead Adder - correct answer ✔This type of addition circuit
develops all carries in logic, directly from the inputs, rather than waiting for
them to propagate from less significant bit positions.
Wallace Tree - correct answer ✔A structure comprised of multiple levels of
carry save adders, which can be used to efficiently implement multiplication.
Excess (biased) Notation - correct answer ✔This type of notation stores
signed numbers as though they
were unsigned; it is used to represent exponents in some floating-point
formats.
Significand (fraction) - correct answer ✔In IEEE-754 floating-point numbers,
a normalized mantissa with the leading 1 omitted is called this.
Positive Infinity - correct answer ✔This is the result when the operation
1.0/0.0 is performed on a system with IEEE-754 floating-point arithmetic.
Instruction Register (IR) - correct answer ✔This holds the currently executing
machine language
instruction so its bits can be decoded and interpreted by the control unit.
Microroutine - correct answer ✔A sequence of microinstructions that fetches
or executes a machine language instruction, initiates exception processing, or
carries out some other basic machine-level task.
,Horizontal Microprogramming - correct answer ✔A technique used in
microprogrammed control unit
design in which mutually-exclusive control signals are not encoded into bit
fields, thus eliminating the need for decoding microinstructions.
Flow-Through Time - correct answer ✔The time required for the first result in
a series of computations to emerge from a pipeline.
Pipeline Register - correct answer ✔This is used to separate one stage of a
pipeline from the next.
Pipeline Throughput - correct answer ✔Over time, this tells the mean
number of operations completed per clock cycle.
Branch Penalty - correct answer ✔The clock cycles that are wasted by an
instruction-pipelined processor due to executing a control transfer instruction.
Static Branch Prediction - correct answer ✔A technique used in pipelined
CPUs where the compiler supplies a hint as to whether or not a given
conditional branch is likely to succeed.
Delay Slot Instruction(s) - correct answer ✔The instruction(s) immediately
following a conditional
control transfer instruction in some pipelined processors, which are executed
whether or not the control transfer occurs.
Delayed Load - correct answer ✔A technique used in pipelined CPUs where
the instruction immediately following another instruction that reads a memory
operand cannot use the updated value
of the operand.
, Read After Write (RAW) Hazard - correct answer ✔The most common data
hazard in pipelined
processors; also known as a true data dependence.
Write After Write (WAW) Hazard - correct answer ✔Also known as an output
dependence, this hazard
can occur in a processor that utilizes out-of-order execution.
Scoreboard - correct answer ✔A centralized resource scheduling
mechanism for internally concurrent processors; it was first used in the CDC
6600 supercomputer.
Reservation Stations - correct answer ✔These are used by a Tomasulo
scheduler to hold operands for functional units.
Overlapping Register Windows - correct answer ✔A feature of some
instruction set architectures (e.g. SPARC) that attempts to optimize
application performance by avoiding the use of procedure parameters stored
on stack frames
Superpipelined - correct answer ✔This type of processor architecture
maximizes temporal parallelism by using a very deep pipeline with very fast
stages.
Predication - correct answer ✔The IA-64 architecture uses this approach
instead of branch prediction to minimize the disruption caused by conditional
control transfers.
