WGU C952 5 The Processor questions with verified
answers
Anti-dependence Ans✓✓✓ Also called name dependence. An ordering forced by
the reuse of a name typically a register, rather than by a true dependence that
carries a value between two instructions
Architectural registers Ans✓✓✓ The instruction set of visible registers of a
processor; for example, in LEGv8, these are the 32 integer and 32 floating-point
registers
Asserted Ans✓✓✓ The signal is logically high or true
Branch not taken Ans✓✓✓ A branch where the branch condition is false and the
program counter (PC) becomes the address of the instruction that sequentially
follows the branch.
Branch prediction buffer Ans✓✓✓ Also called branch history table. A small
memory that is indexed by the lower portion of the address of the branch
instruction and that contains one or more bits indicating whether the branch was
recently taken or not.
Branch prediction Ans✓✓✓ A method of resolving a branch hazard that assumes
a given outcome for the branch and proceeds from that assumption rather than
waiting to ascertain the actual outcome.
Branch taken Ans✓✓✓ A branch where the branch condition is satisfied and the
program counter becomes the branch target. All unconditional branches are
taken branches
, Branch target address Ans✓✓✓ the address specified in a branch, which
becomes the new program counter if the branch is taken. In the LEGv8
architecture, it's given by the sum of the offset field of the instruction and the
address of the branch
Branch target buffer Ans✓✓✓ A structure that caches the destination program
counter (PC) or destination instruction for a branch. It is usually organized as a
cache with tags, making it more costly than a simple prediction buffer.
Clocking methodology Ans✓✓✓ The approach used to determine when data is
valid and stable relative to the clock.
Combinational element Ans✓✓✓ An operational element, such as an AND gate
or an ALU.
Commit unit Ans✓✓✓ The unit in a dynamic or out-of-order execution pipeline
that decides when it is safe to release the result of an operation to programmer-
visible registers and memory.
Control hazard Ans✓✓✓ Also called branch hazard. When the proper instruction
cannot execute in the proper pipeline clock cycle because the instruction that was
fetched is not the one that is needed; that is, the flow of instruction addresses is
not what the pipeline expected.
Control signal Ans✓✓✓ A signal used for multiplexor selection or for directing
the operation of a functional unit; contrasts with a data signal, which contains
information that is operated on by a functional unit.
answers
Anti-dependence Ans✓✓✓ Also called name dependence. An ordering forced by
the reuse of a name typically a register, rather than by a true dependence that
carries a value between two instructions
Architectural registers Ans✓✓✓ The instruction set of visible registers of a
processor; for example, in LEGv8, these are the 32 integer and 32 floating-point
registers
Asserted Ans✓✓✓ The signal is logically high or true
Branch not taken Ans✓✓✓ A branch where the branch condition is false and the
program counter (PC) becomes the address of the instruction that sequentially
follows the branch.
Branch prediction buffer Ans✓✓✓ Also called branch history table. A small
memory that is indexed by the lower portion of the address of the branch
instruction and that contains one or more bits indicating whether the branch was
recently taken or not.
Branch prediction Ans✓✓✓ A method of resolving a branch hazard that assumes
a given outcome for the branch and proceeds from that assumption rather than
waiting to ascertain the actual outcome.
Branch taken Ans✓✓✓ A branch where the branch condition is satisfied and the
program counter becomes the branch target. All unconditional branches are
taken branches
, Branch target address Ans✓✓✓ the address specified in a branch, which
becomes the new program counter if the branch is taken. In the LEGv8
architecture, it's given by the sum of the offset field of the instruction and the
address of the branch
Branch target buffer Ans✓✓✓ A structure that caches the destination program
counter (PC) or destination instruction for a branch. It is usually organized as a
cache with tags, making it more costly than a simple prediction buffer.
Clocking methodology Ans✓✓✓ The approach used to determine when data is
valid and stable relative to the clock.
Combinational element Ans✓✓✓ An operational element, such as an AND gate
or an ALU.
Commit unit Ans✓✓✓ The unit in a dynamic or out-of-order execution pipeline
that decides when it is safe to release the result of an operation to programmer-
visible registers and memory.
Control hazard Ans✓✓✓ Also called branch hazard. When the proper instruction
cannot execute in the proper pipeline clock cycle because the instruction that was
fetched is not the one that is needed; that is, the flow of instruction addresses is
not what the pipeline expected.
Control signal Ans✓✓✓ A signal used for multiplexor selection or for directing
the operation of a functional unit; contrasts with a data signal, which contains
information that is operated on by a functional unit.
