CEA 201 CORRECT EXAMS SCRIPT QUESTIONS AND
ANSWERS SET A+
✔✔T - ✔✔Computer systems contain a number of different buses that provide pathways
between components at various levels of the computer system hierarchy.
(T/F)
✔✔T - ✔✔In general, the more devices attached to the bus, the greater the bus length
and hence the greater the propagation delay.
(T/F)
✔✔F - ✔✔It is not possible to connect I/O controllers directly onto the system bus.
(T/F)
✔✔T - ✔✔The method of using the same lines for multiple purposes is known as time
multiplexing.
(T/F)
✔✔T - ✔✔Timing refers to the way in which events are coordinated on the bus.
(T/F)
✔✔F - ✔✔With asynchronous timing the occurrence of events on the bus is determined
by a clock.
(T/F)
✔✔T - ✔✔Because all devices on a synchronous bus are tied to a fixed clock rate, the
system cannot take advantage of advances in device performance.
(T/F)
✔✔F - ✔✔The unit of transfer at the link layer is a phit and the unit transfer at the
physical layer is a flit.
(T/F)
,✔✔T - ✔✔A key requirement for PCIe is high capacity to support the needs of higher
data rate I/O devices such as Gigabit Ethernet.
(T/F)
✔✔B - ✔✔Virtually all contemporary computer designs are based on concepts
developed by __________ at the Institute for Advanced Studies, Princeton.
A. John Maulchy
B. John von Neumann
C. Herman Hollerith
D. John Eckert
✔✔D - ✔✔The von Neumann architecture is based on which concept?
A. Data and instructions are stored in a single read-write memory
B. The contents of this memory are addressable by location
C. Execution occurs in a sequential fashion
D. All of the above
✔✔A - ✔✔A sequence of codes or instructions is called __________.
A. Software
B. Memory
C. An interconnect
D. A register
✔✔C - ✔✔The processing required for a single instruction is called a(n) __________
cycle.
A. Execute
B. Fetch
C. Instruction
D. Packet
✔✔B - ✔✔A(n) _________ is generated by a failure such as power failure or memory
parity error.
A. I/O interrupt
B. Hardware failure interrupt
C. Timer interrupt
D. Program interrupt
✔✔C - ✔✔A(n) _________ is generated by some condition that occurs as a result of an
instruction execution.
A. Timer interrupt
B. I/O interrupt
C. Program interrupt
D. Hardware failure interrupt
,✔✔D - ✔✔The interconnection structure must support which transfer?
A. Memory to processor
B. Processor to memory
C. I/O to or from memory
D. All of the above
✔✔A - ✔✔A bus that connects major computer components (processor, memory, I/O) is
called a __________.
A. System bus
B. Address bus
C. Data bus
D. Control bus
✔✔D - ✔✔The __________ are used to designate the source or destination of the data
on the data bus.
A. System lines
B. Data lines
C. Control lines
D. Address lines
✔✔C - ✔✔The data lines provide a path for moving data among system modules and
are collectively called the _________.
A. Control bus
B. Address bus
C. Data bus
D. System bus
✔✔B - ✔✔A __________ is the high-level set of rules for exchanging packets of data
between devices.
A. Bus
B. Protocol
C. Packet
D. QPI
✔✔A - ✔✔Each data path consists of a pair of wires (referred to as a __________) that
transmits data one bit at a time.
A. Lane
B. Path
C. Line
D. Bus
✔✔A - ✔✔The _________ receives read and write requests from the software above
the TL and creates request packets for transmission to a destination via the link layer.
A. Transaction layer
B. Root layer
, C. Configuration layer
D. Transport layer
✔✔D - ✔✔The TL supports which of the following address spaces?
A. Memory
B. I/O
C. Message
D. All of the above
✔✔C - ✔✔The QPI _________ layer is used to determine the course that a packet will
traverse across the available system interconnects.
A. Link
B. Protocol
C. Routing
D. Physical
✔✔T - ✔✔No single technology is optimal in satisfying the memory requirements for a
computer system.
(T/F)
✔✔T - ✔✔A typical computer system is equipped with a hierarchy of memory
subsystems, some internal to the system and some external.
(T/F)
✔✔F - ✔✔External memory is often equated with main memory.
(T/F)
✔✔T - ✔✔The processor requires its own local memory.
(T/F)
✔✔F - ✔✔Cache is not a form of internal memory.
(T/F)
✔✔F - ✔✔The unit of transfer must equal a word or an addressable unit.
(T/F)
✔✔T - ✔✔Both sequential access and direct access involve a shared read-write
mechanism.
(T/F)
✔✔T - ✔✔In a volatile memory, information decays naturally or is lost when electrical
power is switched off.
(T/F)
ANSWERS SET A+
✔✔T - ✔✔Computer systems contain a number of different buses that provide pathways
between components at various levels of the computer system hierarchy.
(T/F)
✔✔T - ✔✔In general, the more devices attached to the bus, the greater the bus length
and hence the greater the propagation delay.
(T/F)
✔✔F - ✔✔It is not possible to connect I/O controllers directly onto the system bus.
(T/F)
✔✔T - ✔✔The method of using the same lines for multiple purposes is known as time
multiplexing.
(T/F)
✔✔T - ✔✔Timing refers to the way in which events are coordinated on the bus.
(T/F)
✔✔F - ✔✔With asynchronous timing the occurrence of events on the bus is determined
by a clock.
(T/F)
✔✔T - ✔✔Because all devices on a synchronous bus are tied to a fixed clock rate, the
system cannot take advantage of advances in device performance.
(T/F)
✔✔F - ✔✔The unit of transfer at the link layer is a phit and the unit transfer at the
physical layer is a flit.
(T/F)
,✔✔T - ✔✔A key requirement for PCIe is high capacity to support the needs of higher
data rate I/O devices such as Gigabit Ethernet.
(T/F)
✔✔B - ✔✔Virtually all contemporary computer designs are based on concepts
developed by __________ at the Institute for Advanced Studies, Princeton.
A. John Maulchy
B. John von Neumann
C. Herman Hollerith
D. John Eckert
✔✔D - ✔✔The von Neumann architecture is based on which concept?
A. Data and instructions are stored in a single read-write memory
B. The contents of this memory are addressable by location
C. Execution occurs in a sequential fashion
D. All of the above
✔✔A - ✔✔A sequence of codes or instructions is called __________.
A. Software
B. Memory
C. An interconnect
D. A register
✔✔C - ✔✔The processing required for a single instruction is called a(n) __________
cycle.
A. Execute
B. Fetch
C. Instruction
D. Packet
✔✔B - ✔✔A(n) _________ is generated by a failure such as power failure or memory
parity error.
A. I/O interrupt
B. Hardware failure interrupt
C. Timer interrupt
D. Program interrupt
✔✔C - ✔✔A(n) _________ is generated by some condition that occurs as a result of an
instruction execution.
A. Timer interrupt
B. I/O interrupt
C. Program interrupt
D. Hardware failure interrupt
,✔✔D - ✔✔The interconnection structure must support which transfer?
A. Memory to processor
B. Processor to memory
C. I/O to or from memory
D. All of the above
✔✔A - ✔✔A bus that connects major computer components (processor, memory, I/O) is
called a __________.
A. System bus
B. Address bus
C. Data bus
D. Control bus
✔✔D - ✔✔The __________ are used to designate the source or destination of the data
on the data bus.
A. System lines
B. Data lines
C. Control lines
D. Address lines
✔✔C - ✔✔The data lines provide a path for moving data among system modules and
are collectively called the _________.
A. Control bus
B. Address bus
C. Data bus
D. System bus
✔✔B - ✔✔A __________ is the high-level set of rules for exchanging packets of data
between devices.
A. Bus
B. Protocol
C. Packet
D. QPI
✔✔A - ✔✔Each data path consists of a pair of wires (referred to as a __________) that
transmits data one bit at a time.
A. Lane
B. Path
C. Line
D. Bus
✔✔A - ✔✔The _________ receives read and write requests from the software above
the TL and creates request packets for transmission to a destination via the link layer.
A. Transaction layer
B. Root layer
, C. Configuration layer
D. Transport layer
✔✔D - ✔✔The TL supports which of the following address spaces?
A. Memory
B. I/O
C. Message
D. All of the above
✔✔C - ✔✔The QPI _________ layer is used to determine the course that a packet will
traverse across the available system interconnects.
A. Link
B. Protocol
C. Routing
D. Physical
✔✔T - ✔✔No single technology is optimal in satisfying the memory requirements for a
computer system.
(T/F)
✔✔T - ✔✔A typical computer system is equipped with a hierarchy of memory
subsystems, some internal to the system and some external.
(T/F)
✔✔F - ✔✔External memory is often equated with main memory.
(T/F)
✔✔T - ✔✔The processor requires its own local memory.
(T/F)
✔✔F - ✔✔Cache is not a form of internal memory.
(T/F)
✔✔F - ✔✔The unit of transfer must equal a word or an addressable unit.
(T/F)
✔✔T - ✔✔Both sequential access and direct access involve a shared read-write
mechanism.
(T/F)
✔✔T - ✔✔In a volatile memory, information decays naturally or is lost when electrical
power is switched off.
(T/F)
