CEA 201 STUDYS LATEST QUESTIONS AND ANSWERS
SET A+
✔✔A - ✔✔The ________ determines the opcode and the operand specifiers.
A. decode instruction
B. fetch operands
C. calculate operands
D. execute instruction
✔✔D - ✔✔_________ is a pipeline hazard.
A. Control
B. Resource
C. Data
D. All of the above
✔✔B - ✔✔A ________ hazard occurs when there is a conflict in the access of an
operand location.
A. resource
B. data
C. structural
D. control
✔✔A - ✔✔A _________ is a small, very-high-speed memory maintained by the
instruction fetch stage of the pipeline and containing the n most recently fetched
instructions in sequence.
A. loop buffer
B. delayed branch
C. multiple stream
D. branch prediction
✔✔C - ✔✔The _________ is a small cache memory associated with the instruction
fetch stage of the pipeline.
A. dynamic branch
,B. loop table
C. branch history table
D. flag
✔✔B - ✔✔The _________ stage includes ALU operations, cache access, and register
update.
A. decode
B. execute
C. fetch
D. write back
✔✔C - ✔✔________ is used for debugging.
A. Direction flag
B. Alignment check
C. Trap flag
D. Identification flag
✔✔D - ✔✔The ARM architecture supports _______ execution modes.
A. 2
B. 8
C. 11
D. 7
✔✔A - ✔✔The OS usually runs in ________.
A. supervisor mode
B. abort mode
C. undefined mode
D. fast interrupt mode
✔✔T - ✔✔Microprogramming eases the task of designing and implementing the control
unit and provides support for the family concept.
(T/F)
✔✔T - ✔✔Pipelining is a means of introducing parallelism into the essentially sequential
nature of a machine-instruction program.
(T/F)
✔✔F - ✔✔The major cost in the life cycle of a system is hardware.
(T/F)
✔✔T - ✔✔It is common for programs, both system and application, to continue to exhibit
new bugs after years of operation.
(T/F)
✔✔F - ✔✔Procedure calls and returns are not important aspects of HLL programs.
, (T/F)
✔✔T - ✔✔The register file is on the same chip as the ALU and control unit.
(T/F)
✔✔T - ✔✔The register file employs much shorter addresses than addresses for cache
and memory.
(T/F)
✔✔T - ✔✔To handle any possible pattern of calls and returns the number of register
windows would have to be unbounded.
(T/F)
✔✔F - ✔✔Cache memory is a much faster memory than the register file.
(T/F)
✔✔T - ✔✔The cache is capable of handling global as well as local variables.
(T/F)
✔✔T - ✔✔With simple, one cycle instructions, there is little or no need for microcode.
(T/F)
✔✔F - ✔✔When using graph coloring, nodes that share the same color cannot be
assigned to the same register.
(T/F)
✔✔T - ✔✔Almost all RISC instructions use simple register addressing.
(T/F)
✔✔T - ✔✔RISC processors are more responsive to interrupts because interrupts are
checked between rather elementary operations.
(T/F)
✔✔T - ✔✔Unrolling can improve performance by increasing instruction parallelism by
improving pipeline performance.
(T/F)
✔✔B - ✔✔_________ determines the control and pipeline organization.
A. Calculation
B. Execution sequencing
C. Operations performed
D. Operands used
✔✔A - ✔✔The Patterson study examined the dynamic behavior of _________
programs, independent of the underlying architecture.
SET A+
✔✔A - ✔✔The ________ determines the opcode and the operand specifiers.
A. decode instruction
B. fetch operands
C. calculate operands
D. execute instruction
✔✔D - ✔✔_________ is a pipeline hazard.
A. Control
B. Resource
C. Data
D. All of the above
✔✔B - ✔✔A ________ hazard occurs when there is a conflict in the access of an
operand location.
A. resource
B. data
C. structural
D. control
✔✔A - ✔✔A _________ is a small, very-high-speed memory maintained by the
instruction fetch stage of the pipeline and containing the n most recently fetched
instructions in sequence.
A. loop buffer
B. delayed branch
C. multiple stream
D. branch prediction
✔✔C - ✔✔The _________ is a small cache memory associated with the instruction
fetch stage of the pipeline.
A. dynamic branch
,B. loop table
C. branch history table
D. flag
✔✔B - ✔✔The _________ stage includes ALU operations, cache access, and register
update.
A. decode
B. execute
C. fetch
D. write back
✔✔C - ✔✔________ is used for debugging.
A. Direction flag
B. Alignment check
C. Trap flag
D. Identification flag
✔✔D - ✔✔The ARM architecture supports _______ execution modes.
A. 2
B. 8
C. 11
D. 7
✔✔A - ✔✔The OS usually runs in ________.
A. supervisor mode
B. abort mode
C. undefined mode
D. fast interrupt mode
✔✔T - ✔✔Microprogramming eases the task of designing and implementing the control
unit and provides support for the family concept.
(T/F)
✔✔T - ✔✔Pipelining is a means of introducing parallelism into the essentially sequential
nature of a machine-instruction program.
(T/F)
✔✔F - ✔✔The major cost in the life cycle of a system is hardware.
(T/F)
✔✔T - ✔✔It is common for programs, both system and application, to continue to exhibit
new bugs after years of operation.
(T/F)
✔✔F - ✔✔Procedure calls and returns are not important aspects of HLL programs.
, (T/F)
✔✔T - ✔✔The register file is on the same chip as the ALU and control unit.
(T/F)
✔✔T - ✔✔The register file employs much shorter addresses than addresses for cache
and memory.
(T/F)
✔✔T - ✔✔To handle any possible pattern of calls and returns the number of register
windows would have to be unbounded.
(T/F)
✔✔F - ✔✔Cache memory is a much faster memory than the register file.
(T/F)
✔✔T - ✔✔The cache is capable of handling global as well as local variables.
(T/F)
✔✔T - ✔✔With simple, one cycle instructions, there is little or no need for microcode.
(T/F)
✔✔F - ✔✔When using graph coloring, nodes that share the same color cannot be
assigned to the same register.
(T/F)
✔✔T - ✔✔Almost all RISC instructions use simple register addressing.
(T/F)
✔✔T - ✔✔RISC processors are more responsive to interrupts because interrupts are
checked between rather elementary operations.
(T/F)
✔✔T - ✔✔Unrolling can improve performance by increasing instruction parallelism by
improving pipeline performance.
(T/F)
✔✔B - ✔✔_________ determines the control and pipeline organization.
A. Calculation
B. Execution sequencing
C. Operations performed
D. Operands used
✔✔A - ✔✔The Patterson study examined the dynamic behavior of _________
programs, independent of the underlying architecture.
