WGU D686 OPERATING SYSTEMS FOR COMPUTER SCIENTISTS –
OBJECTIVE ASSESSMENT 2 (2026)
1. Which process state transition is possible only after an I/O event completes?
- A) Running → Ready
- B) Running → Blocked
- C) Blocked → Ready
- D) Ready → Running
Answer: C) Blocked → Ready
Rationale: A process in the Blocked state is waiting for an I/O event. Once the I/O finishes, the process
moves to the Ready queue. The other transitions occur due to timer interrupts, preemption, or
scheduling, not I/O completion.
2. In a round‑robin scheduler with a time quantum of 10 ms and a context‑switch time of 1 ms, what is
the CPU efficiency?
- A) 90.9 %
- B) 91 %
- C) 90 %
- D) 10 %
Answer: A) 90.9 %
Rationale: Efficiency = quantum / (quantum + switch) = 10 / (10 + 1) = ≈ 90.9 %.
3. Which scheduling algorithm minimizes the average waiting time?
- A) First‑Come, First‑Served (FCFS)
- B) Shortest Job First (SJF, non‑preemptive)
- C) Round‑Robin (RR)
- D) Priority scheduling
,Answer: B) Shortest Job First (SJF, non‑preemptive)
Rationale: SJF provably yields the minimum average waiting time for a given set of processes. FCFS may
cause the convoy effect, RR adds context‑switch overhead, and priority scheduling can cause starvation.
4. Which component of the CPU performs arithmetic operations such as addition, subtraction, and
logical comparisons (AND, OR, NOT)?
- A) Control Unit (CU)
- B) Arithmetic Logic Unit (ALU)
- C) Register
- D) Cache
Answer: B) Arithmetic Logic Unit (ALU)
Rationale: The ALU is the part of the CPU responsible for all arithmetic and logic operations. The Control
Unit directs data flow, registers hold temporary data, and cache speeds up memory access.
5. Which CPU component manages and coordinates the execution of instructions, including controlling
data flow between the CPU and memory?
- A) ALU
- B) Control Unit (CU)
- C) Program Counter
- D) Memory Management Unit
Answer: B) Control Unit (CU)
Rationale: The Control Unit decodes instructions and generates control signals that orchestrate the
movement of data between the CPU, memory, and I/O devices.
6. Small, high‑speed storage locations inside the CPU that temporarily hold data and instructions being
processed are called:
- A) Registers
- B) Cache lines
,- C) RAM cells
- D) Stack frames
Answer: A) Registers
Rationale: Registers are the fastest memory elements in the CPU, used to store operands, intermediate
results, and memory addresses during instruction execution.
7. A CPU design technique that breaks instruction execution into stages so that multiple instructions can
be processed simultaneously at different stages is called:
- A) Parallelism
- B) Hyper‑threading
- C) Pipelining
- D) Superscalar
Answer: C) Pipelining
Rationale: Pipelining increases instruction throughput by overlapping the fetch, decode, execute, and
write‑back stages of several instructions.
8. Which type of memory is volatile, used to load applications and the operating system, and holds the
OS system code while the computer is running?
- A) ROM
- B) Flash memory
- C) RAM
- D) Cache
Answer: C) RAM
Rationale: RAM is the main volatile memory that stores currently executing programs and OS code. It
loses its content when power is removed.
, 9. Which cache is the smallest, fastest, and integrated directly into the CPU core?
- A) L1 cache
- B) L2 cache
- C) L3 cache
- D) L4 cache
Answer: A) L1 cache
Rationale: L1 cache is the smallest and fastest cache, typically split into instruction and data caches, and
resides inside each CPU core.
10. Which cache level is larger than L1 but slower, and may reside outside the CPU core (or on‑chip but
per‑core)?
- A) L1 cache
- B) L2 cache
- C) L3 cache
- D) L4 cache
Answer: B) L2 cache
Rationale: L2 cache is larger than L1 and is often still very fast. In modern CPUs, L2 is usually on‑chip but
may be dedicated to each core.
11. Which cache is the largest and slowest among the on‑chip caches and is typically shared among all
CPU cores?
OBJECTIVE ASSESSMENT 2 (2026)
1. Which process state transition is possible only after an I/O event completes?
- A) Running → Ready
- B) Running → Blocked
- C) Blocked → Ready
- D) Ready → Running
Answer: C) Blocked → Ready
Rationale: A process in the Blocked state is waiting for an I/O event. Once the I/O finishes, the process
moves to the Ready queue. The other transitions occur due to timer interrupts, preemption, or
scheduling, not I/O completion.
2. In a round‑robin scheduler with a time quantum of 10 ms and a context‑switch time of 1 ms, what is
the CPU efficiency?
- A) 90.9 %
- B) 91 %
- C) 90 %
- D) 10 %
Answer: A) 90.9 %
Rationale: Efficiency = quantum / (quantum + switch) = 10 / (10 + 1) = ≈ 90.9 %.
3. Which scheduling algorithm minimizes the average waiting time?
- A) First‑Come, First‑Served (FCFS)
- B) Shortest Job First (SJF, non‑preemptive)
- C) Round‑Robin (RR)
- D) Priority scheduling
,Answer: B) Shortest Job First (SJF, non‑preemptive)
Rationale: SJF provably yields the minimum average waiting time for a given set of processes. FCFS may
cause the convoy effect, RR adds context‑switch overhead, and priority scheduling can cause starvation.
4. Which component of the CPU performs arithmetic operations such as addition, subtraction, and
logical comparisons (AND, OR, NOT)?
- A) Control Unit (CU)
- B) Arithmetic Logic Unit (ALU)
- C) Register
- D) Cache
Answer: B) Arithmetic Logic Unit (ALU)
Rationale: The ALU is the part of the CPU responsible for all arithmetic and logic operations. The Control
Unit directs data flow, registers hold temporary data, and cache speeds up memory access.
5. Which CPU component manages and coordinates the execution of instructions, including controlling
data flow between the CPU and memory?
- A) ALU
- B) Control Unit (CU)
- C) Program Counter
- D) Memory Management Unit
Answer: B) Control Unit (CU)
Rationale: The Control Unit decodes instructions and generates control signals that orchestrate the
movement of data between the CPU, memory, and I/O devices.
6. Small, high‑speed storage locations inside the CPU that temporarily hold data and instructions being
processed are called:
- A) Registers
- B) Cache lines
,- C) RAM cells
- D) Stack frames
Answer: A) Registers
Rationale: Registers are the fastest memory elements in the CPU, used to store operands, intermediate
results, and memory addresses during instruction execution.
7. A CPU design technique that breaks instruction execution into stages so that multiple instructions can
be processed simultaneously at different stages is called:
- A) Parallelism
- B) Hyper‑threading
- C) Pipelining
- D) Superscalar
Answer: C) Pipelining
Rationale: Pipelining increases instruction throughput by overlapping the fetch, decode, execute, and
write‑back stages of several instructions.
8. Which type of memory is volatile, used to load applications and the operating system, and holds the
OS system code while the computer is running?
- A) ROM
- B) Flash memory
- C) RAM
- D) Cache
Answer: C) RAM
Rationale: RAM is the main volatile memory that stores currently executing programs and OS code. It
loses its content when power is removed.
, 9. Which cache is the smallest, fastest, and integrated directly into the CPU core?
- A) L1 cache
- B) L2 cache
- C) L3 cache
- D) L4 cache
Answer: A) L1 cache
Rationale: L1 cache is the smallest and fastest cache, typically split into instruction and data caches, and
resides inside each CPU core.
10. Which cache level is larger than L1 but slower, and may reside outside the CPU core (or on‑chip but
per‑core)?
- A) L1 cache
- B) L2 cache
- C) L3 cache
- D) L4 cache
Answer: B) L2 cache
Rationale: L2 cache is larger than L1 and is often still very fast. In modern CPUs, L2 is usually on‑chip but
may be dedicated to each core.
11. Which cache is the largest and slowest among the on‑chip caches and is typically shared among all
CPU cores?
