WGU C952 Objective Assessment Computer
Architecture Actual Exam –2026-
2028Questions with Answers and Rationales
(Full-Length Study Guide) | pdf
1. A computer system uses a CPU with a 32-bit address bus. What is the
maximum amount of addressable memory?
A. 2 GB
B. 4 GB
C. 8 GB
D. 16 GB
Rationale:: A 32-bit address bus can address 2³² memory locations = 4 GB.
2. During the fetch-decode-execute cycle, which step involves interpreting the
instruction?
A. Fetch
B. Execute
C. Decode
D. Store
Rationale:: The decode phase determines what operation the instruction
specifies.
3. Which component of the CPU performs arithmetic and logical operations?
A. Control Unit
B. Register File
,C. Arithmetic Logic Unit (ALU)
D. Cache
Rationale:: The ALU handles calculations and logical comparisons.
4. A system has a cache hit rate of 95%. What does this indicate?
A. Cache is unused
B. Cache is slow
C. 95% of memory accesses are found in cache
D. Cache is failing
Rationale:: Hit rate refers to how often requested data is found in cache.
5. Which memory type is volatile?
A. ROM
B. SSD
C. HDD
D. RAM
Rationale:: RAM loses data when power is removed.
6. What is the purpose of the program counter (PC)?
A. Store instructions
B. Execute instructions
C. Hold address of next instruction
D. Perform arithmetic
Rationale:: PC tracks the next instruction to fetch.
7. Which type of memory is fastest?
, A. HDD
B. RAM
C. SSD
D. Registers
Rationale:: Registers are located inside the CPU and are the fastest.
8. What does pipelining improve?
A. Memory size
B. Clock speed
C. Instruction throughput
D. Storage capacity
Rationale:: Pipelining allows multiple instructions to overlap execution.
9. What is a cache miss?
A. Data found in cache
B. Cache failure
C. Requested data not found in cache
D. Memory corruption
Rationale:: Cache miss means data must be fetched from slower memory.
10. Which bus carries data between CPU and memory?
A. Address bus
B. Control bus
C. Data bus
D. Expansion bus
Rationale:: The data bus transfers actual data.
Architecture Actual Exam –2026-
2028Questions with Answers and Rationales
(Full-Length Study Guide) | pdf
1. A computer system uses a CPU with a 32-bit address bus. What is the
maximum amount of addressable memory?
A. 2 GB
B. 4 GB
C. 8 GB
D. 16 GB
Rationale:: A 32-bit address bus can address 2³² memory locations = 4 GB.
2. During the fetch-decode-execute cycle, which step involves interpreting the
instruction?
A. Fetch
B. Execute
C. Decode
D. Store
Rationale:: The decode phase determines what operation the instruction
specifies.
3. Which component of the CPU performs arithmetic and logical operations?
A. Control Unit
B. Register File
,C. Arithmetic Logic Unit (ALU)
D. Cache
Rationale:: The ALU handles calculations and logical comparisons.
4. A system has a cache hit rate of 95%. What does this indicate?
A. Cache is unused
B. Cache is slow
C. 95% of memory accesses are found in cache
D. Cache is failing
Rationale:: Hit rate refers to how often requested data is found in cache.
5. Which memory type is volatile?
A. ROM
B. SSD
C. HDD
D. RAM
Rationale:: RAM loses data when power is removed.
6. What is the purpose of the program counter (PC)?
A. Store instructions
B. Execute instructions
C. Hold address of next instruction
D. Perform arithmetic
Rationale:: PC tracks the next instruction to fetch.
7. Which type of memory is fastest?
, A. HDD
B. RAM
C. SSD
D. Registers
Rationale:: Registers are located inside the CPU and are the fastest.
8. What does pipelining improve?
A. Memory size
B. Clock speed
C. Instruction throughput
D. Storage capacity
Rationale:: Pipelining allows multiple instructions to overlap execution.
9. What is a cache miss?
A. Data found in cache
B. Cache failure
C. Requested data not found in cache
D. Memory corruption
Rationale:: Cache miss means data must be fetched from slower memory.
10. Which bus carries data between CPU and memory?
A. Address bus
B. Control bus
C. Data bus
D. Expansion bus
Rationale:: The data bus transfers actual data.
