ECE 6913 Final (Section A) Exam Questions and 100% Correct Answers (Verified
Answers) 2026 Q&A Latest- NYU
1. One difference between a write-through cache and a write-back cache can be in the time it takes to write.
During the first cycle, we detect whether a hit will occur, and during the second (assuming a hit) we
actually write the data.
Let’s assume that 30% of the blocks are dirty for a write-back cache. For this question, assume that the
write buffer for the write through will never stall the CPU (no penalty). Assume a cache read hit takes 1
clock cycle, the cache miss penalty is 100 clock cycles, and a block write from the cache to main memory
takes 50 clock cycles. Finally, assume the instruction cache miss rate is 0.5% and the data cache miss rate
is 2%. Assume that on average 25% and 10% of instructions in the workload are loads and stores,
respectively.
Estimate the performance of a write-through cache with a two-cycle write versus a write-back cache with
a two-cycle write
CPU performance equation: CPUTime = IC ∗ CPI ∗ ClockTime CPI =
CPIexecution + StallCyclesPerInstruction
We know:
Instruction miss penalty is 50 cycles Data
read hit takes 1 cycle
Data write hit takes 2 cycles
Data miss penalty is 100 cycles for write through cache
Data miss penalty is 100 cycles or 150 cycles for write back cache
Miss rate is 2% for data cache (MRD) and 0.5% for instruction cache (MRI) 30% of
cache blocks are dirty in the write back cache
25% of all instructions are loads 10%
of all instructions are stores
Then: CPIexecution = 0.25 ∗ 1 + 0.10 ∗ 2 + 0.65 ∗ 1 = 1.1
Write through
StallCyclesPerInstruction = 0.5% ∗ 50 + 2% ∗ (0.25 ∗ 100 + 0.10 ∗ 100) = 0.95
so: CPI = 1.1 + 0.95 = 2.05 (1)
Write back
StallCyclesPerInstruction = 0.5% ∗ 50 + 2% ∗ (0.25 ∗ (0.3 ∗ 100 + 0.3 ∗ 150) + 0.10 ∗
(0.3 ∗ 100 + 0.3 ∗ 150)) = 0.775
so: CP I = 1.1 + 0.775 = 1.875 (2)
Comparing 1 and 2 we notice that the system with the write back cache is 6% slower.
2. Assume that we have an N-way set associative cache that has a block size of 8 bytes and the number of
sets is 256. Assume that the replacement policy is least recently used (LRU).
(a) If the capacity of the cache is 8192 bytes, what is then the associativity of the cache?
Given that the cache capacity is 8192 bytes, the block size is 8 bytes, and the number of sets is 256, we can
calculate the associativity as follows:
, Associativity = (Cache Capacity) / (Block Size * Number of Sets)
= 8192 bytes / (8 bytes * 256)
= 4 ways
Therefore, the associativity of the cache is 4 ways.
(b) Sketch the layout of the cache content for the cache if we assume that N = 2. The figure should include
the ways and columns for the valid bit, the tag, and the data. What is then the capacity of the cache?
Way 0 Way 1
| Valid | Tag | Data || Valid | Tag | Data |
| | | || | | |
| | | || | | |
| | | || | | |
| | | || | | |
| | | || | | |
| | | || | | |
| | | || | | |
| | | || | | |
As we can see, each set in the cache contains two blocks, one in each way. Each block has a valid bit, a tag, and the
data that corresponds to the memory block stored in the cache.
To calculate the capacity of the cache, we need to multiply the block size by the number of blocks in the cache,
which is equal to the product of the number of sets, the number of ways, and the number of blocks per set:
Capacity = Block Size * Number of Sets * Number of Ways * Blocks per Set
= 8 bytes * 256 sets * 2 ways * 1 block per set
= 4096 bytes
Therefore, the capacity of the cache is 4096 bytes.
3. Suppose a computer using fully associative cache has 224 words of main memory, and a cache of 128
blocks, where each cache block contains 64 words
(a) How many blocks of main memory are there?
224/26 = 218
(b) What are the sizes of the tag and word fields?
24 bit addresses with 18 bits in the tag field and 6 in the word field
Answers) 2026 Q&A Latest- NYU
1. One difference between a write-through cache and a write-back cache can be in the time it takes to write.
During the first cycle, we detect whether a hit will occur, and during the second (assuming a hit) we
actually write the data.
Let’s assume that 30% of the blocks are dirty for a write-back cache. For this question, assume that the
write buffer for the write through will never stall the CPU (no penalty). Assume a cache read hit takes 1
clock cycle, the cache miss penalty is 100 clock cycles, and a block write from the cache to main memory
takes 50 clock cycles. Finally, assume the instruction cache miss rate is 0.5% and the data cache miss rate
is 2%. Assume that on average 25% and 10% of instructions in the workload are loads and stores,
respectively.
Estimate the performance of a write-through cache with a two-cycle write versus a write-back cache with
a two-cycle write
CPU performance equation: CPUTime = IC ∗ CPI ∗ ClockTime CPI =
CPIexecution + StallCyclesPerInstruction
We know:
Instruction miss penalty is 50 cycles Data
read hit takes 1 cycle
Data write hit takes 2 cycles
Data miss penalty is 100 cycles for write through cache
Data miss penalty is 100 cycles or 150 cycles for write back cache
Miss rate is 2% for data cache (MRD) and 0.5% for instruction cache (MRI) 30% of
cache blocks are dirty in the write back cache
25% of all instructions are loads 10%
of all instructions are stores
Then: CPIexecution = 0.25 ∗ 1 + 0.10 ∗ 2 + 0.65 ∗ 1 = 1.1
Write through
StallCyclesPerInstruction = 0.5% ∗ 50 + 2% ∗ (0.25 ∗ 100 + 0.10 ∗ 100) = 0.95
so: CPI = 1.1 + 0.95 = 2.05 (1)
Write back
StallCyclesPerInstruction = 0.5% ∗ 50 + 2% ∗ (0.25 ∗ (0.3 ∗ 100 + 0.3 ∗ 150) + 0.10 ∗
(0.3 ∗ 100 + 0.3 ∗ 150)) = 0.775
so: CP I = 1.1 + 0.775 = 1.875 (2)
Comparing 1 and 2 we notice that the system with the write back cache is 6% slower.
2. Assume that we have an N-way set associative cache that has a block size of 8 bytes and the number of
sets is 256. Assume that the replacement policy is least recently used (LRU).
(a) If the capacity of the cache is 8192 bytes, what is then the associativity of the cache?
Given that the cache capacity is 8192 bytes, the block size is 8 bytes, and the number of sets is 256, we can
calculate the associativity as follows:
, Associativity = (Cache Capacity) / (Block Size * Number of Sets)
= 8192 bytes / (8 bytes * 256)
= 4 ways
Therefore, the associativity of the cache is 4 ways.
(b) Sketch the layout of the cache content for the cache if we assume that N = 2. The figure should include
the ways and columns for the valid bit, the tag, and the data. What is then the capacity of the cache?
Way 0 Way 1
| Valid | Tag | Data || Valid | Tag | Data |
| | | || | | |
| | | || | | |
| | | || | | |
| | | || | | |
| | | || | | |
| | | || | | |
| | | || | | |
| | | || | | |
As we can see, each set in the cache contains two blocks, one in each way. Each block has a valid bit, a tag, and the
data that corresponds to the memory block stored in the cache.
To calculate the capacity of the cache, we need to multiply the block size by the number of blocks in the cache,
which is equal to the product of the number of sets, the number of ways, and the number of blocks per set:
Capacity = Block Size * Number of Sets * Number of Ways * Blocks per Set
= 8 bytes * 256 sets * 2 ways * 1 block per set
= 4096 bytes
Therefore, the capacity of the cache is 4096 bytes.
3. Suppose a computer using fully associative cache has 224 words of main memory, and a cache of 128
blocks, where each cache block contains 64 words
(a) How many blocks of main memory are there?
224/26 = 218
(b) What are the sizes of the tag and word fields?
24 bit addresses with 18 bits in the tag field and 6 in the word field
