COMPUTER ARCHITECTURE 2026 –
PROCESSOR DESIGN & MEMORY
SYSTEMS VERIFIED EXAM GUIDE
Q1. What does the CPU stand for?
A) Central Processing Unit
B) Central Program Utility
C) Core Processing Unit
D) Central Peripheral Unit
✔ CORRECT ANSWER: A RATIONALE: CPU stands for Central Processing Unit —
the primary component that executes instructions in a computer system.
Q2. Which component of the CPU performs arithmetic and logical operations?
A) Control Unit
B) Registers
C) Arithmetic Logic Unit (ALU)
D) Cache Memory
✔ CORRECT ANSWER: C RATIONALE: The ALU handles all arithmetic (addition,
subtraction) and logical (AND, OR, NOT) operations within the CPU.
Q3. The program counter (PC) holds:
A) The result of the last arithmetic operation
B) The address of the next instruction to be executed
C) The current instruction being decoded
D) The stack pointer address
✔ CORRECT ANSWER: B RATIONALE: The Program Counter always points to the
memory address of the next instruction the CPU will fetch.
,Q4. Which bus carries data between the CPU and memory?
A) Address Bus
B) Control Bus
C) Data Bus
D) Instruction Bus
✔ CORRECT ANSWER: C RATIONALE: The Data Bus is bidirectional and transfers
actual data between the CPU, memory, and I/O devices.
Q5. What is the function of the control unit?
A) Performs calculations
B) Stores data temporarily
C) Directs operations of the processor
D) Manages cache memory
✔ CORRECT ANSWER: C RATIONALE: The Control Unit interprets instructions and
generates signals to coordinate the operation of all CPU components.
Q6. Von Neumann architecture is characterized by:
A) Separate memory for instructions and data
B) A shared memory for both instructions and data
C) Multiple processors working in parallel
D) Harvard architecture principles
✔ CORRECT ANSWER: B RATIONALE: Von Neumann architecture uses a single
shared memory for both program instructions and data, which can lead to the "Von Neumann
bottleneck."
Q7. Harvard architecture differs from Von Neumann in that it:
A) Uses a single bus
,B) Has no cache
C) Separates instruction memory from data memory
D) Has no ALU
✔ CORRECT ANSWER: C RATIONALE: Harvard architecture uses physically separate
storage and buses for instructions and data, allowing simultaneous access to both.
Q8. Which register holds the current instruction being executed?
A) Program Counter
B) Stack Pointer
C) Instruction Register
D) Memory Address Register
✔ CORRECT ANSWER: C RATIONALE: The Instruction Register (IR) holds the
instruction currently being decoded and executed by the CPU.
Q9. The memory address register (MAR) contains:
A) The data to be stored in memory
B) The address of the memory location being accessed
C) The last instruction executed
D) The current stack frame
✔ CORRECT ANSWER: B RATIONALE: The MAR holds the address of the memory
location that the CPU wants to read from or write to.
Q10. What is the fetch-decode-execute cycle?
A) A memory access pattern
B) The basic operational steps of a CPU
C) A cache replacement algorithm
D) A pipeline stage
, ✔ CORRECT ANSWER: B RATIONALE: The fetch-decode-execute cycle describes the
fundamental process by which a CPU retrieves an instruction from memory, decodes it, and
executes it.
Q11. Which of the following best describes clock speed?
A) The amount of RAM in a system
B) The number of instructions per second
C) The frequency at which the CPU executes cycles
D) The data transfer rate of the bus
✔ CORRECT ANSWER: C RATIONALE: Clock speed, measured in Hz (GHz),
determines how many cycles per second a CPU can perform, directly affecting processing speed.
Q12. What does RISC stand for?
A) Reduced Instruction Set Computer
B) Rapid Instruction Set Computing
C) Reduced Internal Storage Computer
D) Random Instruction Set Computer
✔ CORRECT ANSWER: A RATIONALE: RISC stands for Reduced Instruction Set
Computer — a CPU design philosophy that uses simple, fixed-length instructions executable in a
single clock cycle.
Q13. What does CISC stand for?
A) Complex Internal Storage Computer
B) Complex Instruction Set Computer
C) Central Instruction Set Computer
D) Complex Integrated Storage Controller
PROCESSOR DESIGN & MEMORY
SYSTEMS VERIFIED EXAM GUIDE
Q1. What does the CPU stand for?
A) Central Processing Unit
B) Central Program Utility
C) Core Processing Unit
D) Central Peripheral Unit
✔ CORRECT ANSWER: A RATIONALE: CPU stands for Central Processing Unit —
the primary component that executes instructions in a computer system.
Q2. Which component of the CPU performs arithmetic and logical operations?
A) Control Unit
B) Registers
C) Arithmetic Logic Unit (ALU)
D) Cache Memory
✔ CORRECT ANSWER: C RATIONALE: The ALU handles all arithmetic (addition,
subtraction) and logical (AND, OR, NOT) operations within the CPU.
Q3. The program counter (PC) holds:
A) The result of the last arithmetic operation
B) The address of the next instruction to be executed
C) The current instruction being decoded
D) The stack pointer address
✔ CORRECT ANSWER: B RATIONALE: The Program Counter always points to the
memory address of the next instruction the CPU will fetch.
,Q4. Which bus carries data between the CPU and memory?
A) Address Bus
B) Control Bus
C) Data Bus
D) Instruction Bus
✔ CORRECT ANSWER: C RATIONALE: The Data Bus is bidirectional and transfers
actual data between the CPU, memory, and I/O devices.
Q5. What is the function of the control unit?
A) Performs calculations
B) Stores data temporarily
C) Directs operations of the processor
D) Manages cache memory
✔ CORRECT ANSWER: C RATIONALE: The Control Unit interprets instructions and
generates signals to coordinate the operation of all CPU components.
Q6. Von Neumann architecture is characterized by:
A) Separate memory for instructions and data
B) A shared memory for both instructions and data
C) Multiple processors working in parallel
D) Harvard architecture principles
✔ CORRECT ANSWER: B RATIONALE: Von Neumann architecture uses a single
shared memory for both program instructions and data, which can lead to the "Von Neumann
bottleneck."
Q7. Harvard architecture differs from Von Neumann in that it:
A) Uses a single bus
,B) Has no cache
C) Separates instruction memory from data memory
D) Has no ALU
✔ CORRECT ANSWER: C RATIONALE: Harvard architecture uses physically separate
storage and buses for instructions and data, allowing simultaneous access to both.
Q8. Which register holds the current instruction being executed?
A) Program Counter
B) Stack Pointer
C) Instruction Register
D) Memory Address Register
✔ CORRECT ANSWER: C RATIONALE: The Instruction Register (IR) holds the
instruction currently being decoded and executed by the CPU.
Q9. The memory address register (MAR) contains:
A) The data to be stored in memory
B) The address of the memory location being accessed
C) The last instruction executed
D) The current stack frame
✔ CORRECT ANSWER: B RATIONALE: The MAR holds the address of the memory
location that the CPU wants to read from or write to.
Q10. What is the fetch-decode-execute cycle?
A) A memory access pattern
B) The basic operational steps of a CPU
C) A cache replacement algorithm
D) A pipeline stage
, ✔ CORRECT ANSWER: B RATIONALE: The fetch-decode-execute cycle describes the
fundamental process by which a CPU retrieves an instruction from memory, decodes it, and
executes it.
Q11. Which of the following best describes clock speed?
A) The amount of RAM in a system
B) The number of instructions per second
C) The frequency at which the CPU executes cycles
D) The data transfer rate of the bus
✔ CORRECT ANSWER: C RATIONALE: Clock speed, measured in Hz (GHz),
determines how many cycles per second a CPU can perform, directly affecting processing speed.
Q12. What does RISC stand for?
A) Reduced Instruction Set Computer
B) Rapid Instruction Set Computing
C) Reduced Internal Storage Computer
D) Random Instruction Set Computer
✔ CORRECT ANSWER: A RATIONALE: RISC stands for Reduced Instruction Set
Computer — a CPU design philosophy that uses simple, fixed-length instructions executable in a
single clock cycle.
Q13. What does CISC stand for?
A) Complex Internal Storage Computer
B) Complex Instruction Set Computer
C) Central Instruction Set Computer
D) Complex Integrated Storage Controller
