correctly solved 2025/2026
The single-cycle implementation for the addu instructions uses the components in the following order:
(include MUXs in the correct order, you can ignore sign-extension.)
(Select the answer from the drop down options, only one correct.
If the number of Functional units is less than 8, you can select None for the remaining (last) blanks)
PC -> Instruction Memory -> MUX -> Register File -> ALU -> ALU -> MUX -> Register File -> None - correct
answer Instruction Memory, MUX, Register File, MUX, ALU, MUX, Register File, None
For the instruction beq $s1, $s1, Label the value for PCSrc is: - correct answer 1
Use this instruction mix, R-Type = 25%, I(not lw/sw/b) = 22%, lw= 23%, sw = 15%, bne/beq = 10%, j = 5%
The values 0, 1 and x for the control signals should be considered separately.
What is the percentage of instructions that have "0" for RegWrite control signal?
(Only write the number, do not write the % symbol) - correct answer 30
Use this instruction mix, R-Type = 25%, I(not lw/sw/b) = 22%, lw= 23%, sw = 15%, bne/beq = 10%, j = 5%
The values 0, 1 and x for the control signals should be considered separately.
What is the percentage of instructions that have "01" for ALUOp control signal?
(Only write the number, do not write the % symbol) - correct answer 10
Given:
Memory unit - 5ns
Register File - 1ns
, ALU - 2ns
Start: sw $s0, 0($s1)
addi $s1, $s1, 4
beq $s1, $s2, Start
What is the equation for Execution Time of the program? Hint type instuction *(Number of iterations in
the loop) - correct answer (20+20+15)*(#loop)
Execution Time for the following program:Start: addi $s1, $s2, 8Loop: lw $s0, 0($s1)addi $s1, $s1, -4bne
$s1, $s2, Loop
Given: Memory Unit - 3 ns
Register File - 2 ns
ALU - 2.5 ns
Hint: Find Execution time of Program = Execution time * Number of times executed - correct answer 84
ns
Which of the following mapping between instructions and number of clock cyclesfor the completion of
the instruction are true (one or more correct)?
Add - 4 clock cycle
Lw - 5 clock cycles
Sw - 1 clock cycle
J - 3 clock cycles
Bne - 2 clock cycles - correct answer Add - 4 clock cycle
Lw - 5 clock cycles
J - 3 clock cycles