ECE 200
Digital Logic Design
Final Exam Review
(Questions & Solutions)
2025
1
, Section I – Multiple Choice (8 Questions)
1. In digital logic design, which gate is considered _universal_ because
any Boolean function can be implemented using only that gate?
A. AND
B. OR
C. NAND
D. XOR
ANS: C
Rationale: The NAND gate is universal, meaning that any Boolean
function can be constructed solely using NAND gates. This makes it a
cornerstone in digital circuit synthesis.
---
2. Which of the following Boolean algebra laws states that a variable
ORed with its complement yields 1?
A. Identity Law
B. Null Law
C. Complementarity Law
D. Absorption Law
ANS: C
Rationale: The Complementarity Law (or Inverse Law) states that for
any Boolean variable X, \( X + X' = 1 \). This fundamental relationship is
critical in many minimization and simplification procedures.
---
3. In a 4-variable Karnaugh map, what is the maximum size of a
grouping (or "implicant") that can be formed to simplify a Boolean
expression?
2
, A. 2 cells
B. 4 cells
C. 8 cells
D. 16 cells
ANS: D
Rationale: A 4-variable K-map contains 16 cells. The largest grouping
possible is an octet (8 cells) when adjacent ones allow, but because cells
wrap around, in some cases the entire map might simplify a function.
However, for standard Boolean function minimization, groups are formed
in powers of 2 with 16 being the total. (Note: Typically, groups are limited
to powers of 2 up to 16; the most common maximum grouping is 8. In
this question, the “maximum size” refers to the full K-map size, but the
standard ANS is “16 cells”; however, in practice, groupings must be
rectangular and may not always cover all 16, so here the best ANS is D.)
---
4. Which element best differentiates a synchronous sequential circuit
from an asynchronous one?
A. The type of logic gates used
B. The presence of a common clock signal to control all state changes
C. The use of combinational logic only
D. The physical layout on a chip
ANS: B
Rationale: Synchronous sequential circuits use a clock signal to
coordinate all state transitions simultaneously, while asynchronous
circuits update immediately upon changes in input without a clock.
---
5. What is the main function of a multiplexer in digital logic systems?
A. To store data temporarily
B. To convert analog signals to digital
3
Digital Logic Design
Final Exam Review
(Questions & Solutions)
2025
1
, Section I – Multiple Choice (8 Questions)
1. In digital logic design, which gate is considered _universal_ because
any Boolean function can be implemented using only that gate?
A. AND
B. OR
C. NAND
D. XOR
ANS: C
Rationale: The NAND gate is universal, meaning that any Boolean
function can be constructed solely using NAND gates. This makes it a
cornerstone in digital circuit synthesis.
---
2. Which of the following Boolean algebra laws states that a variable
ORed with its complement yields 1?
A. Identity Law
B. Null Law
C. Complementarity Law
D. Absorption Law
ANS: C
Rationale: The Complementarity Law (or Inverse Law) states that for
any Boolean variable X, \( X + X' = 1 \). This fundamental relationship is
critical in many minimization and simplification procedures.
---
3. In a 4-variable Karnaugh map, what is the maximum size of a
grouping (or "implicant") that can be formed to simplify a Boolean
expression?
2
, A. 2 cells
B. 4 cells
C. 8 cells
D. 16 cells
ANS: D
Rationale: A 4-variable K-map contains 16 cells. The largest grouping
possible is an octet (8 cells) when adjacent ones allow, but because cells
wrap around, in some cases the entire map might simplify a function.
However, for standard Boolean function minimization, groups are formed
in powers of 2 with 16 being the total. (Note: Typically, groups are limited
to powers of 2 up to 16; the most common maximum grouping is 8. In
this question, the “maximum size” refers to the full K-map size, but the
standard ANS is “16 cells”; however, in practice, groupings must be
rectangular and may not always cover all 16, so here the best ANS is D.)
---
4. Which element best differentiates a synchronous sequential circuit
from an asynchronous one?
A. The type of logic gates used
B. The presence of a common clock signal to control all state changes
C. The use of combinational logic only
D. The physical layout on a chip
ANS: B
Rationale: Synchronous sequential circuits use a clock signal to
coordinate all state transitions simultaneously, while asynchronous
circuits update immediately upon changes in input without a clock.
---
5. What is the main function of a multiplexer in digital logic systems?
A. To store data temporarily
B. To convert analog signals to digital
3
