IT 105 Computer Architecture
Comprehensive Final Exam (Qns & Ans)
2025
Question 1 (Multiple Choice)
Question:
Which of the following best characterizes the primary objective of
Very Long Instruction Word (VLIW) architectures?
A) To use a fixed instruction length that simplifies decoding
regardless of instruction complexity.
B) To enable dynamic hardware scheduling by allowing
instructions to flow out of order.
C) To exploit instruction-level parallelism by packing multiple
independent operations into one long instruction word.
D) To minimize power consumption through reduced clock
frequencies.
©2025
, Correct ANS:
C) To exploit instruction-level parallelism by packing multiple
independent operations into one long instruction word.
Rationale:
VLIW architectures are designed to explicitly encode multiple
operations in a single, long instruction word. This design relies on
the compiler to schedule and pack independent instructions that
can execute in parallel, thereby maximizing instruction-level
parallelism without complex hardware scheduling.
---
Question 2 (Fill in the Blank)
Question:
The processor’s ability to execute parts of different instructions
simultaneously by overlapping their execution stages is known as
________ .
Correct ANS:
instruction-level parallelism
Rationale:
©2025
,Instruction-level parallelism (ILP) allows a processor to execute
multiple instructions concurrently, typically by exploiting parallel
execution units and overlapping instruction stages (fetch, decode,
execute, etc.) within a pipeline. This is critical for increasing
throughput in modern CPUs.
---
Question 3 (True/False)
Question:
True/False: A superscalar processor can issue and execute
multiple instructions per clock cycle by incorporating several
parallel execution units.
Correct ANS:
True
Rationale:
Superscalar architectures are designed to issue multiple
instructions each cycle by using several execution units
concurrently. This parallel execution improves throughput and
overall performance, provided that the instructions are
independent and the necessary hardware resources are available.
©2025
, ---
Question 4 (Multiple Response)
Question:
Select all of the following techniques that effectively reduce
pipeline hazards in modern processors:
A) Register renaming
B) Dynamic scheduling
C) Branch prediction
D) Increased instruction cache size
E) Compiler optimization
Correct ANS:
A, B, C, E
Rationale:
Register renaming eliminates false data dependencies, dynamic
scheduling allows instructions to execute as soon as operands are
ready, branch prediction minimizes control hazards, and compiler
optimization can reorder instructions to reduce stalls. Increasing
the instruction cache size, while beneficial for performance, does
not directly mitigate pipeline hazards.
©2025
Comprehensive Final Exam (Qns & Ans)
2025
Question 1 (Multiple Choice)
Question:
Which of the following best characterizes the primary objective of
Very Long Instruction Word (VLIW) architectures?
A) To use a fixed instruction length that simplifies decoding
regardless of instruction complexity.
B) To enable dynamic hardware scheduling by allowing
instructions to flow out of order.
C) To exploit instruction-level parallelism by packing multiple
independent operations into one long instruction word.
D) To minimize power consumption through reduced clock
frequencies.
©2025
, Correct ANS:
C) To exploit instruction-level parallelism by packing multiple
independent operations into one long instruction word.
Rationale:
VLIW architectures are designed to explicitly encode multiple
operations in a single, long instruction word. This design relies on
the compiler to schedule and pack independent instructions that
can execute in parallel, thereby maximizing instruction-level
parallelism without complex hardware scheduling.
---
Question 2 (Fill in the Blank)
Question:
The processor’s ability to execute parts of different instructions
simultaneously by overlapping their execution stages is known as
________ .
Correct ANS:
instruction-level parallelism
Rationale:
©2025
,Instruction-level parallelism (ILP) allows a processor to execute
multiple instructions concurrently, typically by exploiting parallel
execution units and overlapping instruction stages (fetch, decode,
execute, etc.) within a pipeline. This is critical for increasing
throughput in modern CPUs.
---
Question 3 (True/False)
Question:
True/False: A superscalar processor can issue and execute
multiple instructions per clock cycle by incorporating several
parallel execution units.
Correct ANS:
True
Rationale:
Superscalar architectures are designed to issue multiple
instructions each cycle by using several execution units
concurrently. This parallel execution improves throughput and
overall performance, provided that the instructions are
independent and the necessary hardware resources are available.
©2025
, ---
Question 4 (Multiple Response)
Question:
Select all of the following techniques that effectively reduce
pipeline hazards in modern processors:
A) Register renaming
B) Dynamic scheduling
C) Branch prediction
D) Increased instruction cache size
E) Compiler optimization
Correct ANS:
A, B, C, E
Rationale:
Register renaming eliminates false data dependencies, dynamic
scheduling allows instructions to execute as soon as operands are
ready, branch prediction minimizes control hazards, and compiler
optimization can reorder instructions to reduce stalls. Increasing
the instruction cache size, while beneficial for performance, does
not directly mitigate pipeline hazards.
©2025
