CS – ICSC 3120 C952 Computer Architecture
Complete Final Assessment (Qns & Ans)
2025
Question 1 (Multiple Choice)
Case:
A processor design team is developing a new CPU that can
execute instructions out-of‑order to maximize the use of available
functional units while preserving program semantics. They need a
mechanism that dynamically schedules instructions based on
resource availability and data dependencies.
Question:
Which technique best enables instructions to be executed
out‑of‑order without violating data dependencies?
A. Static instruction scheduling
B. Dynamic scheduling
©2025
,C. In‑order issue with pipeline stalling
D. Single‑issue execution
Correct ANS: B. Dynamic scheduling
Rationale:
Dynamic scheduling allows the hardware to analyze data
dependencies at runtime and schedule instructions out‑of‑order
based on operand availability. This technique increases utilization
of execution units and overall throughput without compromising
the logical order of results.
---
Question 2 (Fill in the Blank)
Case:
A performance analyst is measuring the efficiency of a
processor’s instruction execution. One critical metric is the
average number of instructions executed per clock cycle.
Statement:
The metric commonly used to represent the average number of
instructions executed per clock cycle is called ______.
©2025
, Correct ANS: IPC
Rationale:
IPC (Instructions Per Cycle) quantifies how many instructions a
processor executes, on average, during each clock cycle. It is a
key performance metric used to evaluate the effectiveness of
architectural enhancements.
---
Question 3 (True/False)
Case:
Modern processors often employ speculative execution to
improve performance by pre‑executing instructions based on
predicted branch outcomes.
Statement:
Speculative execution allows a processor to pre‑execute
instructions along the predicted branch path, but if the prediction
is incorrect, the results are discarded and the correct path is
executed.
©2025
, Correct ANS: True
Rationale:
Speculative execution improves performance by keeping pipelines
full. When a branch prediction is wrong, the erroneous work is
undone (flushed) and the correct path is processed, which is why
handling mispredictions efficiently is critical in modern
architectures.
---
Question 4 (Multiple Response)
Case:
A computer architect is addressing data hazards in a pipelined
CPU. Several hardware techniques can mitigate stalls due to data
dependencies.
Question:
Which of the following techniques are commonly used to handle
data hazards in pipelined processors? (Select all that apply.)
A. Operand forwarding
B. Pipeline stalling
C. Register renaming
©2025
Complete Final Assessment (Qns & Ans)
2025
Question 1 (Multiple Choice)
Case:
A processor design team is developing a new CPU that can
execute instructions out-of‑order to maximize the use of available
functional units while preserving program semantics. They need a
mechanism that dynamically schedules instructions based on
resource availability and data dependencies.
Question:
Which technique best enables instructions to be executed
out‑of‑order without violating data dependencies?
A. Static instruction scheduling
B. Dynamic scheduling
©2025
,C. In‑order issue with pipeline stalling
D. Single‑issue execution
Correct ANS: B. Dynamic scheduling
Rationale:
Dynamic scheduling allows the hardware to analyze data
dependencies at runtime and schedule instructions out‑of‑order
based on operand availability. This technique increases utilization
of execution units and overall throughput without compromising
the logical order of results.
---
Question 2 (Fill in the Blank)
Case:
A performance analyst is measuring the efficiency of a
processor’s instruction execution. One critical metric is the
average number of instructions executed per clock cycle.
Statement:
The metric commonly used to represent the average number of
instructions executed per clock cycle is called ______.
©2025
, Correct ANS: IPC
Rationale:
IPC (Instructions Per Cycle) quantifies how many instructions a
processor executes, on average, during each clock cycle. It is a
key performance metric used to evaluate the effectiveness of
architectural enhancements.
---
Question 3 (True/False)
Case:
Modern processors often employ speculative execution to
improve performance by pre‑executing instructions based on
predicted branch outcomes.
Statement:
Speculative execution allows a processor to pre‑execute
instructions along the predicted branch path, but if the prediction
is incorrect, the results are discarded and the correct path is
executed.
©2025
, Correct ANS: True
Rationale:
Speculative execution improves performance by keeping pipelines
full. When a branch prediction is wrong, the erroneous work is
undone (flushed) and the correct path is processed, which is why
handling mispredictions efficiently is critical in modern
architectures.
---
Question 4 (Multiple Response)
Case:
A computer architect is addressing data hazards in a pipelined
CPU. Several hardware techniques can mitigate stalls due to data
dependencies.
Question:
Which of the following techniques are commonly used to handle
data hazards in pipelined processors? (Select all that apply.)
A. Operand forwarding
B. Pipeline stalling
C. Register renaming
©2025
