Dd Exam 3 Latest Questions With 100% Verified Answers!!

DD EXAM 3 LATEST QUESTIONS WITH
100% VERIFIED ANSWERS!!




1 of 37

Term



During FPGA synthesis, a bus with 4 sources connected by 4
tristates gets replaced by an 8x1 mux.



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FIFO Dual Flop




False JAL

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2 of 37

Term


Create a VHDL type my_array for a one-dimensional unconstrained
array where each element is 16 bits



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type my_array is array (natural
type my_array (0 to 99) of
range <>) of
std_logic_vector(31 downto 0);
std_logic_vector(15 downto 0);




The output is either the previous
signal array1 : my_array(0 to 99);
value or the correct value, but never
an incorrect value


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3 of 37

Term


Create a signal array1 that is an instance of my_array with 100 total
elements



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, signal array1 : my_array(0 to
signal array1 : my_array(0 to 98);
99);




signal array1 : my_array(0 to 100); signal array1 : my_array(1 to 100);



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4 of 37

Term


What are the two situations where metastability is unavoidable?



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only during power-up sequences when using only flip-flops




asynchrounous inputs and synchronous inputs and single clock
clock-domain crossing domains


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