Computer Architecture exam 2 study
guide
1. When a cache write miss occurs, the block containing write allocate
the word to be written is fetched from main
memory (or next level cache) into the cache and
the processor proceeds with the write cycle. This
approach is known as ...
2. The cache replacement algorithm that Least Recently Used
replaces the block in the set that has been in
the cache longest with no reference to it.
3. A portion of a cache line that is used for
tag
addressing purposes.
4. When data is contained in the cache without having to cache hit
go to main memory.
5. A type of computer memory that allows data to be Content-
addressable
retrieved based on its content, rather than its address
memory in memory. It is designed such that when a
bit string is supplied, it searches its entire memory
in parallel for
a match.
6. A cache access method that permits each main mem- Associative
mapping
ory block to be loaded into any line of the cache.
7. The cache replacement algorithm that Least Frequently Used
replaces the block in the set that has
experienced the fewest ref- erences.
8. For this cache write policy, all write
write through
operations are made to main memory as well
as to the cache, ensur- ing that main memory
is always valid.
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, Computer Architecture exam 2 study
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9. A portion of cache memory capable of cache line
holding one block.
10. Deals with supercomputers and their high performance com-
software, es- pecially for scientific
puting
applications that involve large amounts of
data, vector and matrix computation, and the
use of parallel algorithms.
write back
11. The cache write policy where updates are
made only in the cache.
12. A hardware memory management unit (MMU) virtual address
trans- lates each into a physical address in
main memory.
13. This cache inclusion policy dictates that a piece of data exclusive
policy
in one cache is guaranteed not to be found in all
lower levels of caches.
14. A cache access method that is a compromise set-associative
that ex- hibits the strengths of both the direct
and associative approaches while reducing
their disadvantages.
15. This cache inclusion policy dictates that a piece of data inclusive
policy
in one cache is guaranteed to be also found in all
lower levels of caches.
16. The cache access method that maps each Direct mapping
block of main memory into only one
possible cache line.
17. This cache inclusion policy dictates that a piece of data non-inclusiv
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, Computer Architecture exam 2 study
guide
policy
in one cache may or may not be found in lower
levels of caches.
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guide
1. When a cache write miss occurs, the block containing write allocate
the word to be written is fetched from main
memory (or next level cache) into the cache and
the processor proceeds with the write cycle. This
approach is known as ...
2. The cache replacement algorithm that Least Recently Used
replaces the block in the set that has been in
the cache longest with no reference to it.
3. A portion of a cache line that is used for
tag
addressing purposes.
4. When data is contained in the cache without having to cache hit
go to main memory.
5. A type of computer memory that allows data to be Content-
addressable
retrieved based on its content, rather than its address
memory in memory. It is designed such that when a
bit string is supplied, it searches its entire memory
in parallel for
a match.
6. A cache access method that permits each main mem- Associative
mapping
ory block to be loaded into any line of the cache.
7. The cache replacement algorithm that Least Frequently Used
replaces the block in the set that has
experienced the fewest ref- erences.
8. For this cache write policy, all write
write through
operations are made to main memory as well
as to the cache, ensur- ing that main memory
is always valid.
1/
36
,Computer Architecture exam 2 study
guide
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36
, Computer Architecture exam 2 study
guide
9. A portion of cache memory capable of cache line
holding one block.
10. Deals with supercomputers and their high performance com-
software, es- pecially for scientific
puting
applications that involve large amounts of
data, vector and matrix computation, and the
use of parallel algorithms.
write back
11. The cache write policy where updates are
made only in the cache.
12. A hardware memory management unit (MMU) virtual address
trans- lates each into a physical address in
main memory.
13. This cache inclusion policy dictates that a piece of data exclusive
policy
in one cache is guaranteed not to be found in all
lower levels of caches.
14. A cache access method that is a compromise set-associative
that ex- hibits the strengths of both the direct
and associative approaches while reducing
their disadvantages.
15. This cache inclusion policy dictates that a piece of data inclusive
policy
in one cache is guaranteed to be also found in all
lower levels of caches.
16. The cache access method that maps each Direct mapping
block of main memory into only one
possible cache line.
17. This cache inclusion policy dictates that a piece of data non-inclusiv
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, Computer Architecture exam 2 study
guide
policy
in one cache may or may not be found in lower
levels of caches.
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